Commit 1ada9010 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'char-misc-5.8-rc7' of...

Merge tag 'char-misc-5.8-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc into master

Pull char/misc driver fixes from Greg KH:
 "Here are a few small driver fixes for 5.8-rc7

  They include:

   - habanalabs fixes

   - tiny fpga driver fixes

   - /dev/mem fixup from previous changes

   - interconnect driver fixes

   - binder fix

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'char-misc-5.8-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
  interconnect: msm8916: Fix buswidth of pcnoc_s nodes
  interconnect: Do not skip aggregation for disabled paths
  /dev/mem: Add missing memory barriers for devmem_inode
  binder: Don't use mmput() from shrinker function.
  habanalabs: prevent possible out-of-bounds array access
  fpga: dfl: fix bug in port reset handshake
  fpga: dfl: pci: reduce the scope of variable 'ret'
  habanalabs: set 4s timeout for message to device CPU
  habanalabs: set clock gating per engine
  habanalabs: block WREG_BULK packet on PDMA
parents 7f2e231c 92d232d1
Loading
Loading
Loading
Loading
+10 −1
Original line number Diff line number Diff line
@@ -16,7 +16,16 @@ Description: Allow the root user to disable/enable in runtime the clock
                gating mechanism in Gaudi. Due to how Gaudi is built, the
                clock gating needs to be disabled in order to access the
                registers of the TPC and MME engines. This is sometimes needed
                during debug by the user and hence the user needs this option
                during debug by the user and hence the user needs this option.
                The user can supply a bitmask value, each bit represents
                a different engine to disable/enable its clock gating feature.
                The bitmask is composed of 20 bits:
                0  -  7 : DMA channels
                8  - 11 : MME engines
                12 - 19 : TPC engines
                The bit's location of a specific engine can be determined
                using (1 << GAUDI_ENGINE_ID_*). GAUDI_ENGINE_ID_* values
                are defined in uapi habanalabs.h file in enum gaudi_engine_id

What:           /sys/kernel/debug/habanalabs/hl<n>/command_buffers
Date:           Jan 2019
+1 −1
Original line number Diff line number Diff line
@@ -947,7 +947,7 @@ enum lru_status binder_alloc_free_page(struct list_head *item,
		trace_binder_unmap_user_end(alloc, index);
	}
	mmap_read_unlock(mm);
	mmput(mm);
	mmput_async(mm);

	trace_binder_unmap_kernel_start(alloc, index);

+7 −3
Original line number Diff line number Diff line
@@ -814,7 +814,8 @@ static struct inode *devmem_inode;
#ifdef CONFIG_IO_STRICT_DEVMEM
void revoke_devmem(struct resource *res)
{
	struct inode *inode = READ_ONCE(devmem_inode);
	/* pairs with smp_store_release() in devmem_init_inode() */
	struct inode *inode = smp_load_acquire(&devmem_inode);

	/*
	 * Check that the initialization has completed. Losing the race
@@ -1028,8 +1029,11 @@ static int devmem_init_inode(void)
		return rc;
	}

	/* publish /dev/mem initialized */
	WRITE_ONCE(devmem_inode, inode);
	/*
	 * Publish /dev/mem initialized.
	 * Pairs with smp_load_acquire() in revoke_devmem().
	 */
	smp_store_release(&devmem_inode, inode);

	return 0;
}
+2 −1
Original line number Diff line number Diff line
@@ -83,7 +83,8 @@ int __afu_port_disable(struct platform_device *pdev)
	 * on this port and minimum soft reset pulse width has elapsed.
	 * Driver polls port_soft_reset_ack to determine if reset done by HW.
	 */
	if (readq_poll_timeout(base + PORT_HDR_CTRL, v, v & PORT_CTRL_SFTRST,
	if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
			       v & PORT_CTRL_SFTRST_ACK,
			       RST_POLL_INVL, RST_POLL_TIMEOUT)) {
		dev_err(&pdev->dev, "timeout, fail to reset device\n");
		return -ETIMEDOUT;
+2 −1
Original line number Diff line number Diff line
@@ -227,7 +227,6 @@ static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
{
	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	struct dfl_fpga_cdev *cdev = drvdata->cdev;
	int ret = 0;

	if (!num_vfs) {
		/*
@@ -239,6 +238,8 @@ static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
		dfl_fpga_cdev_config_ports_pf(cdev);

	} else {
		int ret;

		/*
		 * before enable SRIOV, put released ports into VF access mode
		 * first of all.
Loading