Commit 1aca9939 authored by Owen Chen's avatar Owen Chen Committed by Stephen Boyd
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clk: mediatek: Add MT6765 clock support



Add MT6765 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.

Signed-off-by: default avatarOwen Chen <owen.chen@mediatek.com>
Signed-off-by: default avatarMars Cheng <mars.cheng@mediatek.com>
Signed-off-by: default avatarMacpaul Lin <macpaul.lin@mediatek.com>
Link: https://lore.kernel.org/r/1582278742-1626-6-git-send-email-macpaul.lin@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent eb7beb65
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@@ -117,6 +117,92 @@ config COMMON_CLK_MT2712_VENCSYS
	---help---
	  This driver supports MediaTek MT2712 vencsys clocks.

config COMMON_CLK_MT6765
       bool "Clock driver for MediaTek MT6765"
       depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
       select COMMON_CLK_MEDIATEK
       default ARCH_MEDIATEK && ARM64
       help
         This driver supports MediaTek MT6765 basic clocks.

config COMMON_CLK_MT6765_AUDIOSYS
       bool "Clock driver for MediaTek MT6765 audiosys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 audiosys clocks.

config COMMON_CLK_MT6765_CAMSYS
       bool "Clock driver for MediaTek MT6765 camsys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 camsys clocks.

config COMMON_CLK_MT6765_GCESYS
       bool "Clock driver for MediaTek MT6765 gcesys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 gcesys clocks.

config COMMON_CLK_MT6765_MMSYS
       bool "Clock driver for MediaTek MT6765 mmsys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 mmsys clocks.

config COMMON_CLK_MT6765_IMGSYS
       bool "Clock driver for MediaTek MT6765 imgsys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 imgsys clocks.

config COMMON_CLK_MT6765_VCODECSYS
       bool "Clock driver for MediaTek MT6765 vcodecsys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 vcodecsys clocks.

config COMMON_CLK_MT6765_MFGSYS
       bool "Clock driver for MediaTek MT6765 mfgsys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 mfgsys clocks.

config COMMON_CLK_MT6765_MIPI0ASYS
       bool "Clock driver for MediaTek MT6765 mipi0asys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 mipi0asys clocks.

config COMMON_CLK_MT6765_MIPI0BSYS
       bool "Clock driver for MediaTek MT6765 mipi0bsys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 mipi0bsys clocks.

config COMMON_CLK_MT6765_MIPI1ASYS
       bool "Clock driver for MediaTek MT6765 mipi1asys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 mipi1asys clocks.

config COMMON_CLK_MT6765_MIPI1BSYS
       bool "Clock driver for MediaTek MT6765 mipi1bsys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 mipi1bsys clocks.

config COMMON_CLK_MT6765_MIPI2ASYS
       bool "Clock driver for MediaTek MT6765 mipi2asys"
       depends on COMMON_CLK_MT6765
      help
         This driver supports MediaTek MT6765 mipi2asys clocks.

config COMMON_CLK_MT6765_MIPI2BSYS
       bool "Clock driver for MediaTek MT6765 mipi2bsys"
       depends on COMMON_CLK_MT6765
       help
         This driver supports MediaTek MT6765 mipi2bsys clocks.

config COMMON_CLK_MT6779
	bool "Clock driver for MediaTek MT6779"
	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o

obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
obj-$(CONFIG_COMMON_CLK_MT6765_IMGSYS) += clk-mt6765-img.o
obj-$(CONFIG_COMMON_CLK_MT6765_MIPI0ASYS) += clk-mt6765-mipi0a.o
obj-$(CONFIG_COMMON_CLK_MT6765_MMSYS) += clk-mt6765-mm.o
obj-$(CONFIG_COMMON_CLK_MT6765_VCODECSYS) += clk-mt6765-vcodec.o
obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
obj-$(CONFIG_COMMON_CLK_MT6779_MMSYS) += clk-mt6779-mm.o
obj-$(CONFIG_COMMON_CLK_MT6779_IMGSYS) += clk-mt6779-img.o
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// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Owen Chen <owen.chen@mediatek.com>
 */

#include <linux/clk-provider.h>
#include <linux/platform_device.h>

#include "clk-mtk.h"
#include "clk-gate.h"

#include <dt-bindings/clock/mt6765-clk.h>

static const struct mtk_gate_regs audio0_cg_regs = {
	.set_ofs = 0x0,
	.clr_ofs = 0x0,
	.sta_ofs = 0x0,
};

static const struct mtk_gate_regs audio1_cg_regs = {
	.set_ofs = 0x4,
	.clr_ofs = 0x4,
	.sta_ofs = 0x4,
};

#define GATE_AUDIO0(_id, _name, _parent, _shift) {	\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &audio0_cg_regs,		\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_ops_no_setclr,	\
	}

#define GATE_AUDIO1(_id, _name, _parent, _shift) {	\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &audio1_cg_regs,		\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_ops_no_setclr,	\
	}

static const struct mtk_gate audio_clks[] = {
	/* AUDIO0 */
	GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_ck", 2),
	GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_engen1_ck", 8),
	GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner",
		    "aud_engen1_ck", 19),
	GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_ck", 24),
	GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_ck", 25),
	GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis",
		    "audio_ck", 26),
	GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_ck", 27),
	/* AUDIO1 */
	GATE_AUDIO1(CLK_AUDIO_I2S1_BCLK, "aud_i2s1_bclk",
		    "audio_ck", 4),
	GATE_AUDIO1(CLK_AUDIO_I2S2_BCLK, "aud_i2s2_bclk",
		    "audio_ck", 5),
	GATE_AUDIO1(CLK_AUDIO_I2S3_BCLK, "aud_i2s3_bclk",
		    "audio_ck", 6),
	GATE_AUDIO1(CLK_AUDIO_I2S4_BCLK, "aud_i2s4_bclk",
		    "audio_ck", 7),
};

static int clk_mt6765_audio_probe(struct platform_device *pdev)
{
	struct clk_onecell_data *clk_data;
	int r;
	struct device_node *node = pdev->dev.of_node;

	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);

	mtk_clk_register_gates(node, audio_clks,
			       ARRAY_SIZE(audio_clks), clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)
		pr_err("%s(): could not register clock provider: %d\n",
		       __func__, r);

	return r;
}

static const struct of_device_id of_match_clk_mt6765_audio[] = {
	{ .compatible = "mediatek,mt6765-audsys", },
	{}
};

static struct platform_driver clk_mt6765_audio_drv = {
	.probe = clk_mt6765_audio_probe,
	.driver = {
		.name = "clk-mt6765-audio",
		.of_match_table = of_match_clk_mt6765_audio,
	},
};

builtin_platform_driver(clk_mt6765_audio_drv);
+74 −0
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// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Owen Chen <owen.chen@mediatek.com>
 */

#include <linux/clk-provider.h>
#include <linux/platform_device.h>

#include "clk-mtk.h"
#include "clk-gate.h"

#include <dt-bindings/clock/mt6765-clk.h>

static const struct mtk_gate_regs cam_cg_regs = {
	.set_ofs = 0x4,
	.clr_ofs = 0x8,
	.sta_ofs = 0x0,
};

#define GATE_CAM(_id, _name, _parent, _shift) {		\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &cam_cg_regs,			\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_ops_setclr,	\
	}

static const struct mtk_gate cam_clks[] = {
	GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "mm_ck", 0),
	GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "mm_ck", 1),
	GATE_CAM(CLK_CAM, "cam", "mm_ck", 6),
	GATE_CAM(CLK_CAMTG, "camtg", "mm_ck", 7),
	GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "mm_ck", 8),
	GATE_CAM(CLK_CAMSV0, "camsv0", "mm_ck", 9),
	GATE_CAM(CLK_CAMSV1, "camsv1", "mm_ck", 10),
	GATE_CAM(CLK_CAMSV2, "camsv2", "mm_ck", 11),
	GATE_CAM(CLK_CAM_CCU, "cam_ccu", "mm_ck", 12),
};

static int clk_mt6765_cam_probe(struct platform_device *pdev)
{
	struct clk_onecell_data *clk_data;
	int r;
	struct device_node *node = pdev->dev.of_node;

	clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);

	mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks), clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)
		pr_err("%s(): could not register clock provider: %d\n",
		       __func__, r);

	return r;
}

static const struct of_device_id of_match_clk_mt6765_cam[] = {
	{ .compatible = "mediatek,mt6765-camsys", },
	{}
};

static struct platform_driver clk_mt6765_cam_drv = {
	.probe = clk_mt6765_cam_probe,
	.driver = {
		.name = "clk-mt6765-cam",
		.of_match_table = of_match_clk_mt6765_cam,
	},
};

builtin_platform_driver(clk_mt6765_cam_drv);
+70 −0
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// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Owen Chen <owen.chen@mediatek.com>
 */

#include <linux/clk-provider.h>
#include <linux/platform_device.h>

#include "clk-mtk.h"
#include "clk-gate.h"

#include <dt-bindings/clock/mt6765-clk.h>

static const struct mtk_gate_regs img_cg_regs = {
	.set_ofs = 0x4,
	.clr_ofs = 0x8,
	.sta_ofs = 0x0,
};

#define GATE_IMG(_id, _name, _parent, _shift) {		\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &img_cg_regs,			\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_ops_setclr,	\
	}

static const struct mtk_gate img_clks[] = {
	GATE_IMG(CLK_IMG_LARB2, "img_larb2", "mm_ck", 0),
	GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_ck", 2),
	GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_ck", 3),
	GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_ck", 4),
	GATE_IMG(CLK_IMG_RSC, "img_rsc", "mm_ck", 5),
};

static int clk_mt6765_img_probe(struct platform_device *pdev)
{
	struct clk_onecell_data *clk_data;
	int r;
	struct device_node *node = pdev->dev.of_node;

	clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);

	mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)
		pr_err("%s(): could not register clock provider: %d\n",
		       __func__, r);

	return r;
}

static const struct of_device_id of_match_clk_mt6765_img[] = {
	{ .compatible = "mediatek,mt6765-imgsys", },
	{}
};

static struct platform_driver clk_mt6765_img_drv = {
	.probe = clk_mt6765_img_probe,
	.driver = {
		.name = "clk-mt6765-img",
		.of_match_table = of_match_clk_mt6765_img,
	},
};

builtin_platform_driver(clk_mt6765_img_drv);
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