Commit 1aae3065 authored by Kai Vehmanen's avatar Kai Vehmanen Committed by Ville Syrjälä
Browse files

drm/i915: Add missing HDMI audio pixel clocks for gen12 



Gen12 hardware supports HDMI audio pixel clocks of 296.7/297Mhz
and 593.4/594Mhz. Add the missing rates and add logic to ignore
them if running on older hardware.

Bspec: 49333
Signed-off-by: default avatarKai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200310162338.9387-1-kai.vehmanen@linux.intel.com
parent 4aea5a9e

drivers/gpu/drm/i915/display/intel_audio.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -149,6 +149,10 @@ static const struct { 
	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },

	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },

	{ 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },

	{ 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },

	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },

	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },

	{ 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },

	{ 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },

	{ 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },

	{ 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },

};

};





/* HDMI N/CTS table */

/* HDMI N/CTS table */
@@ -234,6 +238,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 
/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */

/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */

static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)

static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)

{

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	const struct drm_display_mode *adjusted_mode =

	const struct drm_display_mode *adjusted_mode =

		&crtc_state->hw.adjusted_mode;

		&crtc_state->hw.adjusted_mode;

	int i;

	int i;
@@ -243,6 +248,9 @@ static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_sta 
			break;

			break;

	}

	}





	if (INTEL_GEN(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)

		i = ARRAY_SIZE(hdmi_audio_clock);



	if (i == ARRAY_SIZE(hdmi_audio_clock)) {

	if (i == ARRAY_SIZE(hdmi_audio_clock)) {

		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",

		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",

			      adjusted_mode->crtc_clock);

			      adjusted_mode->crtc_clock);

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -9251,6 +9251,10 @@ enum { 
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_296703	(10 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_297000	(11 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_593407	(12 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_594000	(13 << 16)

#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)

#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)





/* HSW Audio */

/* HSW Audio */

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