Commit 1aaccc40 authored Sep 08, 2017 by Kan Liang Committed by Thomas Gleixner Sep 25, 2017

perf/x86/msr: Add missing CPU IDs



Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well.

Signed-off-by: Kan Liang <Kan.liang@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: ak@linux.intel.com
Cc: peterz@infradead.org
Cc: piotr.luc@intel.com
Cc: harry.pan@intel.com
Cc: srinivas.pandruvada@linux.intel.com
Link: http://lkml.kernel.org/r/20170908213449.6224-2-kan.liang@intel.com

parent b09c146f

arch/x86/events/msr.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -63,6 +63,14 @@ static bool test_intel(int idx)
		case INTEL_FAM6_ATOM_SILVERMONT1:
		case INTEL_FAM6_ATOM_SILVERMONT2:
		case INTEL_FAM6_ATOM_AIRMONT:

		case INTEL_FAM6_ATOM_GOLDMONT:
		case INTEL_FAM6_ATOM_DENVERTON:

		case INTEL_FAM6_ATOM_GEMINI_LAKE:

		case INTEL_FAM6_XEON_PHI_KNL:
		case INTEL_FAM6_XEON_PHI_KNM:
		if (idx == PERF_MSR_SMI)
		return true;
		break;

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