Commit 1aa63ddf authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-misc-next-2020-04-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next 



drm-misc-next for 5.8:

UAPI Changes:

  - drm: error out with EBUSY when device has existing master
  - drm: rework SET_MASTER and DROP_MASTER perm handling

Cross-subsystem Changes:

  - mm: export two symbols from slub/slob
  - fbdev: savage: fix -Wextra build warning
  - video: omap2: Use scnprintf() for avoiding potential buffer overflow

Core Changes:

  - Remove drm_pci.h
  - drm_pci_{alloc/free)() are now legacy
  - Introduce managed DRM resourcesA
  - Allow drivers to subclass struct drm_framebuffer
  - Introduce struct drm_afbc_framebuffer and helpers
  - fbdev: remove return value from generic fbdev setup
  - Introduce simple-encoder helper
  - vram-helpers: set fence on plane
  - dp_mst: ACT timeout improvements
  - dp_mst: Remove drm_dp_mst_has_audio()
  - TTM: ttm_trace_dma_{map/unmap}() cleanups
  - dma-buf: add flag for PCIP2P support
  - EDID: Various improvements
  - Encoder: cleanup semantics of possible_clones and possible_crtcs
  - VBLANK documentation updates
  - Writeback documentation updates

Driver Changes:

  - Convert several drivers to i2c_new_client_device()
  - Drop explicit drm_mode_config_cleanup() calls from drivers
  - Auto-release device structures with drmm_add_final_kfree()
  - Init bfdev console after registering DRM device
  - Make various .debugfs functions return 0 unconditionally; ignore errors
  - video: Use scnprintf() to avoid buffer overflows
  - Convert drivers to simple encoders

  - drm/amdgpu: note that we can handle peer2peer DMA-buf
  - drm/amdgpu: add support for exporting VRAM using DMA-buf v3
  - drm/kirin: Revert change to register connectors
  - drm/lima: Add optional devfreq and cooling device support
  - drm/lima: Various improvements wrt. task handling
  - drm/panel: nt39016: Support multiple modes and 50Hz
  - drm/panel: Support Leadtek LTK050H3146W
  - drm/rockchip: Add support for afbc
  - drm/virtio: Various cleanups
  - drm/hisilicon/hibmc: Enforce 128-byte stride alignment
  - drm/qxl: Fix notify port address of cursor ring buffer
  - drm/sun4i: Improvements to format handling
  - drm/bridge: dw-hdmi: Various improvements

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20200414090738.GA16827@linux-uq9g
parents 774f1eeb 14d0066b

Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Northwest Logic MIPI-DSI controller on i.MX SoCs



maintainers:

  - Guido Gúnther <agx@sigxcpu.org>

  - Robert Chiras <robert.chiras@nxp.com>



description: |

  NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for

  the SOCs NWL MIPI-DSI host controller.



properties:

  compatible:

    const: fsl,imx8mq-nwl-dsi



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



  clocks:

    items:

      - description: DSI core clock

      - description: RX_ESC clock (used in escape mode)

      - description: TX_ESC clock (used in escape mode)

      - description: PHY_REF clock

      - description: LCDIF clock



  clock-names:

    items:

      - const: core

      - const: rx_esc

      - const: tx_esc

      - const: phy_ref

      - const: lcdif



  mux-controls:

    description:

      mux controller node to use for operating the input mux



  phys:

    maxItems: 1

    description:

      A phandle to the phy module representing the DPHY



  phy-names:

    items:

      - const: dphy



  power-domains:

    maxItems: 1



  resets:

    items:

      - description: dsi byte reset line

      - description: dsi dpi reset line

      - description: dsi esc reset line

      - description: dsi pclk reset line



  reset-names:

    items:

      - const: byte

      - const: dpi

      - const: esc

      - const: pclk



  ports:

    type: object

    description:

      A node containing DSI input & output port nodes with endpoint

      definitions as documented in

      Documentation/devicetree/bindings/graph.txt.

    properties:

      port@0:

        type: object

        description:

          Input port node to receive pixel data from the

          display controller. Exactly one endpoint must be

          specified.

        properties:

          '#address-cells':

            const: 1



          '#size-cells':

            const: 0



          endpoint@0:

            description: sub-node describing the input from LCDIF

            type: object



          endpoint@1:

            description: sub-node describing the input from DCSS

            type: object



          reg:

            const: 0



        required:

          - '#address-cells'

          - '#size-cells'

          - reg



        oneOf:

          - required:

              - endpoint@0

          - required:

              - endpoint@1



        additionalProperties: false



      port@1:

        type: object

        description:

          DSI output port node to the panel or the next bridge

          in the chain



      '#address-cells':

        const: 1



      '#size-cells':

        const: 0



    required:

      - '#address-cells'

      - '#size-cells'

      - port@0

      - port@1



    additionalProperties: false



patternProperties:

  "^panel@[0-9]+$":

    type: object



required:

  - '#address-cells'

  - '#size-cells'

  - clock-names

  - clocks

  - compatible

  - interrupts

  - mux-controls

  - phy-names

  - phys

  - ports

  - reg

  - reset-names

  - resets



additionalProperties: false



examples:

 - |



   #include <dt-bindings/clock/imx8mq-clock.h>

   #include <dt-bindings/interrupt-controller/arm-gic.h>

   #include <dt-bindings/reset/imx8mq-reset.h>



   mipi_dsi: mipi_dsi@30a00000 {

              #address-cells = <1>;

              #size-cells = <0>;

              compatible = "fsl,imx8mq-nwl-dsi";

              reg = <0x30A00000 0x300>;

              clocks = <&clk IMX8MQ_CLK_DSI_CORE>,

                       <&clk IMX8MQ_CLK_DSI_AHB>,

                       <&clk IMX8MQ_CLK_DSI_IPG_DIV>,

                       <&clk IMX8MQ_CLK_DSI_PHY_REF>,

                       <&clk IMX8MQ_CLK_LCDIF_PIXEL>;

              clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";

              interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

              mux-controls = <&mux 0>;

              power-domains = <&pgc_mipi>;

              resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,

                       <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,

                       <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,

                       <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;

              reset-names = "byte", "dpi", "esc", "pclk";

              phys = <&dphy>;

              phy-names = "dphy";



              panel@0 {

                      #address-cells = <1>;

                      #size-cells = <0>;

                      compatible = "rocktech,jh057n00900";

                      reg = <0>;

                      port@0 {

                           reg = <0>;

                           panel_in: endpoint {

                                     remote-endpoint = <&mipi_dsi_out>;

                           };

                      };

              };



              ports {

                    #address-cells = <1>;

                    #size-cells = <0>;



                    port@0 {

                           #size-cells = <0>;

                           #address-cells = <1>;

                           reg = <0>;

                           mipi_dsi_in: endpoint@0 {

                                        reg = <0>;

                                        remote-endpoint = <&lcdif_mipi_dsi>;

                           };

                    };

                    port@1 {

                           reg = <1>;

                           mipi_dsi_out: endpoint {

                                         remote-endpoint = <&panel_in>;

                           };

                    };

              };

      };

Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml

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@@ -24,6 +24,8 @@ properties: 
      - boe,tv101wum-n53

        # AUO B101UAN08.3 10.1" WUXGA TFT LCD panel

      - auo,b101uan08.3

        # BOE TV105WUM-NW0 10.5" WUXGA TFT LCD panel

      - boe,tv105wum-nw0



  reg:

    description: the virtual channel number of a DSI peripheral

Documentation/devicetree/bindings/display/panel/display-timings.yaml

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@@ -4,7 +4,7 @@ 
$id: http://devicetree.org/schemas/display/panel/display-timings.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: display timing bindings

title: display timings bindings



maintainers:

  - Thierry Reding <thierry.reding@gmail.com>
@@ -14,7 +14,7 @@ maintainers: 
description: |

  A display panel may be able to handle several display timings,

  with different resolutions.

  The display-timings node makes it possible to specify the timing

  The display-timings node makes it possible to specify the timings

  and to specify the timing that is native for the display.



properties:
@@ -25,8 +25,8 @@ properties: 
    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      The default display timing is the one specified as native-mode.

      If no native-mode is specified then the first node is assumed the

      native mode.

      If no native-mode is specified then the first node is assumed

      to be the native mode.



patternProperties:

  "^timing":

Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.txt

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Feiyang FY07024DI26A30-D 7" MIPI-DSI LCD Panel



Required properties:

- compatible: must be "feiyang,fy07024di26a30d"

- reg: DSI virtual channel used by that screen

- avdd-supply: analog regulator dc1 switch

- dvdd-supply: 3v3 digital regulator

- reset-gpios: a GPIO phandle for the reset pin



Optional properties:

- backlight: phandle for the backlight control.



panel@0 {

	compatible = "feiyang,fy07024di26a30d";

	reg = <0>;

	avdd-supply = <&reg_dc1sw>;

	dvdd-supply = <&reg_dldo2>;

	reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */

	backlight = <&backlight>;

};

Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/panel/feiyang,fy07024di26a30d.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Feiyang FY07024DI26A30-D 7" MIPI-DSI LCD Panel



maintainers:

  - Jagan Teki <jagan@amarulasolutions.com>



allOf:

  - $ref: panel-common.yaml#



properties:

  compatible:

    const: feiyang,fy07024di26a30d



  reg:

    description: DSI virtual channel used by that screen

    maxItems: 1



  avdd-supply:

    description: analog regulator dc1 switch



  dvdd-supply:

    description: 3v3 digital regulator



  reset-gpios: true



  backlight: true



required:

  - compatible

  - reg

  - avdd-supply

  - dvdd-supply

  - reset-gpios



additionalProperties: false



examples:

  - |

    #include <dt-bindings/gpio/gpio.h>



    dsi {

        #address-cells = <1>;

        #size-cells = <0>;



        panel@0 {

            compatible = "feiyang,fy07024di26a30d";

            reg = <0>;

            avdd-supply = <&reg_dc1sw>;

            dvdd-supply = <&reg_dldo2>;

            reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */

            backlight = <&backlight>;

        };

    };

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