Commit 1a9b4993 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "The lion share of this pull request are fixes for clk-related breakage
  caused by other changes during this merge window.  For some platforms
  the fix was as simple as selecting HAVE_CLK, for others like the
  Loongson 2 significant restructuring was required.

  The remainder are changes required to get the Lantiq code to work
  again."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Loongson 2: Sort out clock managment.
  MIPS: Loongson 1: more clk support and add select HAVE_CLK
  MIPS: txx9: Fix redefinition of clk_* by adding select HAVE_CLK
  MIPS: BCM63xx: Fix redefinition of clk_* by adding select HAVE_CLK
  MIPS: AR7: Fix redefinition of clk_* by adding select HAVE_CLK
  MIPS: Lantiq: Platform specific CLK fixup
  MIPS: Lantiq: Add device_tree_init function
  MIPS: Lantiq: Fix interface clock and PCI control register offset
parents 1871e845 95cf1468

arch/mips/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ config AR7 
	select SYS_SUPPORTS_ZBOOT_UART16550

	select ARCH_REQUIRE_GPIOLIB

	select VLYNQ

	select HAVE_CLK

	help

	  Support for the Texas Instruments AR7 System-on-a-Chip

	  family: TNETD7100, 7200 and 7300.
@@ -124,6 +125,7 @@ config BCM63XX 
	select SYS_HAS_EARLY_PRINTK

	select SWAP_IO_SPACE

	select ARCH_REQUIRE_GPIOLIB

	select HAVE_CLK

	help

	 Support for BCM63XX based boards

arch/mips/include/asm/clock.h

+0 −11
Original line number Diff line number Diff line
@@ -50,15 +50,4 @@ void clk_recalc_rate(struct clk *); 
int clk_register(struct clk *);

void clk_unregister(struct clk *);



/* the exported API, in addition to clk_set_rate */

/**

 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter

 * @clk: clock source

 * @rate: desired clock rate in Hz

 * @algo_id: algorithm id to be passed down to ops->set_rate

 *

 * Returns success (0) or negative errno.

 */

int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);



#endif				/* __ASM_MIPS_CLOCK_H */

arch/mips/include/asm/mach-loongson/loongson.h

+0 −1
Original line number Diff line number Diff line
@@ -245,7 +245,6 @@ static inline void do_perfcnt_IRQ(void) 


#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ

#include <linux/cpufreq.h>

extern void loongson2_cpu_wait(void);

extern struct cpufreq_frequency_table loongson2_clockmod_table[];



/* Chip Config */

arch/mips/kernel/cpufreq/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -2,4 +2,4 @@ 
# Makefile for the Linux/MIPS cpufreq.

#



obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o loongson2_clock.o
 
obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o

arch/mips/kernel/cpufreq/loongson2_cpufreq.c

+20 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 


#include <asm/clock.h>



#include <loongson.h>

#include <asm/mach-loongson/loongson.h>



static uint nowait;
@@ -181,6 +181,25 @@ static struct platform_driver platform_driver = { 
	.id_table = platform_device_ids,

};



/*

 * This is the simple version of Loongson-2 wait, Maybe we need do this in

 * interrupt disabled context.

 */



static DEFINE_SPINLOCK(loongson2_wait_lock);



static void loongson2_cpu_wait(void)

{

	unsigned long flags;

	u32 cpu_freq;



	spin_lock_irqsave(&loongson2_wait_lock, flags);

	cpu_freq = LOONGSON_CHIPCFG0;

	LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */

	LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */

	spin_unlock_irqrestore(&loongson2_wait_lock, flags);

}



static int __init cpufreq_init(void)

{

	int ret;

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