Commit 1a895f1d authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Herbert Xu
Browse files

crypto: ccree - use u32 for SRAM addresses 



SRAM addresses are small integer offsets into local SRAM.  Currently
they are stored using a mixture of cc_sram_addr_t (u64), u32, and
dma_addr_t types.

Settle on u32, and remove the cc_sram_addr_t typedefs.
This allows to drop several casts.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 37282f8d

drivers/crypto/ccree/cc_aead.c

+3 −3
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 
#define MAX_NONCE_SIZE CTR_RFC3686_NONCE_SIZE



struct cc_aead_handle {

	cc_sram_addr_t sram_workspace_addr;

	u32 sram_workspace_addr;

	struct list_head aead_list;

};
@@ -797,7 +797,7 @@ static void cc_proc_authen_desc(struct aead_request *areq, 
		 * assoc. + iv + data -compact in one table

		 * if assoclen is ZERO only IV perform

		 */

		cc_sram_addr_t mlli_addr = areq_ctx->assoc.sram_addr;

		u32 mlli_addr = areq_ctx->assoc.sram_addr;

		u32 mlli_nents = areq_ctx->assoc.mlli_nents;



		if (areq_ctx->is_single_pass) {
@@ -1171,7 +1171,7 @@ static void cc_mlli_to_sram(struct aead_request *req, 
	    req_ctx->data_buff_type == CC_DMA_BUF_MLLI ||

	    !req_ctx->is_single_pass) && req_ctx->mlli_params.mlli_len) {

		dev_dbg(dev, "Copy-to-sram: mlli_dma=%08x, mlli_size=%u\n",

			(unsigned int)ctx->drvdata->mlli_sram_addr,

			ctx->drvdata->mlli_sram_addr,

			req_ctx->mlli_params.mlli_len);

		/* Copy MLLI table host-to-sram */

		hw_desc_init(&desc[*seq_size]);

drivers/crypto/ccree/cc_buffer_mgr.h

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ enum cc_sg_cpy_direct { 
};



struct cc_mlli {

	cc_sram_addr_t sram_addr;

	u32 sram_addr;

	unsigned int mapped_nents;

	unsigned int nents; //sg nents

	unsigned int mlli_nents; //mlli nents might be different than the above

drivers/crypto/ccree/cc_cipher.c

+5 −5
Original line number Diff line number Diff line
@@ -745,7 +745,7 @@ static void cc_setup_mlli_desc(struct crypto_tfm *tfm, 
		dev_dbg(dev, " bypass params addr %pad length 0x%X addr 0x%08X\n",

			&req_ctx->mlli_params.mlli_dma_addr,

			req_ctx->mlli_params.mlli_len,

			(unsigned int)ctx_p->drvdata->mlli_sram_addr);

			ctx_p->drvdata->mlli_sram_addr);

		hw_desc_init(&desc[*seq_size]);

		set_din_type(&desc[*seq_size], DMA_DLLI,

			     req_ctx->mlli_params.mlli_dma_addr,
@@ -793,16 +793,16 @@ static void cc_setup_flow_desc(struct crypto_tfm *tfm, 
			     req_ctx->in_mlli_nents, NS_BIT);

		if (req_ctx->out_nents == 0) {

			dev_dbg(dev, " din/dout params addr 0x%08X addr 0x%08X\n",

				(unsigned int)ctx_p->drvdata->mlli_sram_addr,

				(unsigned int)ctx_p->drvdata->mlli_sram_addr);

				ctx_p->drvdata->mlli_sram_addr,

				ctx_p->drvdata->mlli_sram_addr);

			set_dout_mlli(&desc[*seq_size],

				      ctx_p->drvdata->mlli_sram_addr,

				      req_ctx->in_mlli_nents, NS_BIT,

				      (!last_desc ? 0 : 1));

		} else {

			dev_dbg(dev, " din/dout params addr 0x%08X addr 0x%08X\n",

				(unsigned int)ctx_p->drvdata->mlli_sram_addr,

				(unsigned int)ctx_p->drvdata->mlli_sram_addr +

				ctx_p->drvdata->mlli_sram_addr,

				ctx_p->drvdata->mlli_sram_addr +

				(u32)LLI_ENTRY_BYTE_SIZE * req_ctx->in_nents);

			set_dout_mlli(&desc[*seq_size],

				      (ctx_p->drvdata->mlli_sram_addr +

drivers/crypto/ccree/cc_driver.h

+1 −1
Original line number Diff line number Diff line
@@ -139,7 +139,7 @@ struct cc_drvdata { 
	int irq;

	struct completion hw_queue_avail; /* wait for HW queue availability */

	struct platform_device *plat_dev;

	cc_sram_addr_t mlli_sram_addr;

	u32 mlli_sram_addr;

	void *buff_mgr_handle;

	void *cipher_handle;

	void *hash_handle;

drivers/crypto/ccree/cc_hash.c

+10 −11
Original line number Diff line number Diff line
@@ -20,8 +20,8 @@ 
#define CC_SM3_HASH_LEN_SIZE 8



struct cc_hash_handle {

	cc_sram_addr_t digest_len_sram_addr; /* const value in SRAM*/

	cc_sram_addr_t larval_digest_sram_addr;   /* const value in SRAM */

	u32 digest_len_sram_addr;	/* const value in SRAM*/

	u32 larval_digest_sram_addr;   /* const value in SRAM */

	struct list_head hash_list;

};
@@ -429,7 +429,7 @@ static int cc_hash_digest(struct ahash_request *req) 
	bool is_hmac = ctx->is_hmac;

	struct cc_crypto_req cc_req = {};

	struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];

	cc_sram_addr_t larval_digest_addr;

	u32 larval_digest_addr;

	int idx = 0;

	int rc = 0;

	gfp_t flags = cc_gfp_flags(&req->base);
@@ -734,7 +734,7 @@ static int cc_hash_setkey(struct crypto_ahash *ahash, const u8 *key, 
	int digestsize = 0;

	int i, idx = 0, rc = 0;

	struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];

	cc_sram_addr_t larval_addr;

	u32 larval_addr;

	struct device *dev;



	ctx = crypto_ahash_ctx(ahash);
@@ -1868,7 +1868,7 @@ static struct cc_hash_alg *cc_alloc_hash_alg(struct cc_hash_template *template, 
int cc_init_hash_sram(struct cc_drvdata *drvdata)

{

	struct cc_hash_handle *hash_handle = drvdata->hash_handle;

	cc_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr;

	u32 sram_buff_ofs = hash_handle->digest_len_sram_addr;

	unsigned int larval_seq_len = 0;

	struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)];

	bool large_sha_supported = (drvdata->hw_rev >= CC_HW_REV_712);
@@ -1974,7 +1974,7 @@ init_digest_const_err: 
int cc_hash_alloc(struct cc_drvdata *drvdata)

{

	struct cc_hash_handle *hash_handle;

	cc_sram_addr_t sram_buff;

	u32 sram_buff;

	u32 sram_size_to_alloc;

	struct device *dev = drvdata_to_dev(drvdata);

	int rc = 0;
@@ -2266,13 +2266,13 @@ static const void *cc_larval_digest(struct device *dev, u32 mode) 
 *

 * \return u32 The address of the initial digest in SRAM

 */

cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode)

u32 cc_larval_digest_addr(void *drvdata, u32 mode)

{

	struct cc_drvdata *_drvdata = (struct cc_drvdata *)drvdata;

	struct cc_hash_handle *hash_handle = _drvdata->hash_handle;

	struct device *dev = drvdata_to_dev(_drvdata);

	bool sm3_supported = (_drvdata->hw_rev >= CC_HW_REV_713);

	cc_sram_addr_t addr;

	u32 addr;



	switch (mode) {

	case DRV_HASH_NULL:
@@ -2324,12 +2324,11 @@ cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode) 
	return hash_handle->larval_digest_sram_addr;

}



cc_sram_addr_t

cc_digest_len_addr(void *drvdata, u32 mode)

u32 cc_digest_len_addr(void *drvdata, u32 mode)

{

	struct cc_drvdata *_drvdata = (struct cc_drvdata *)drvdata;

	struct cc_hash_handle *hash_handle = _drvdata->hash_handle;

	cc_sram_addr_t digest_len_addr = hash_handle->digest_len_sram_addr;

	u32 digest_len_addr = hash_handle->digest_len_sram_addr;



	switch (mode) {

	case DRV_HASH_SHA1:

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