Commit 1a50ec0b authored by Richard Henderson's avatar Richard Henderson Committed by Will Deacon
Browse files

arm64: Implement archrandom.h for ARMv8.5-RNG 



Expose the ID_AA64ISAR0.RNDR field to userspace, as the RNG system
registers are always available at EL0.

Implement arch_get_random_seed_long using RNDR.  Given that the
TRNG is likely to be a shared resource between cores, and VMs,
do not explicitly force re-seeding with RNDRRS.  In order to avoid
code complexity and potential issues with hetrogenous systems only
provide values after cpufeature has finalized the system capabilities.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
[Modified to only function after cpufeature has finalized the system
capabilities and move all the code into the header -- broonie]
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Reviewed-by: default avatarArd Biesheuvel <ardb@kernel.org>
[will: Advertise HWCAP via /proc/cpuinfo]
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 46cf053e

Documentation/arm64/cpu-feature-registers.rst

+2 −0
Original line number Diff line number Diff line
@@ -117,6 +117,8 @@ infrastructure: 
     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | RNDR                         | [63-60] |    y    |

     +------------------------------+---------+---------+

     | TS                           | [55-52] |    y    |

     +------------------------------+---------+---------+

     | FHM                          | [51-48] |    y    |

Documentation/arm64/elf_hwcaps.rst

+4 −0
Original line number Diff line number Diff line
@@ -204,6 +204,10 @@ HWCAP2_FRINT 


    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.



HWCAP2_RNG



    Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.





4. Unused AT_HWCAP bits

-----------------------

arch/arm64/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -1484,6 +1484,18 @@ config ARM64_PTR_AUTH 


endmenu



menu "ARMv8.5 architectural features"



config ARCH_RANDOM

	bool "Enable support for random number generation"

	default y

	help

	  Random number generation (part of the ARMv8.5 Extensions)

	  provides a high bandwidth, cryptographically secure

	  hardware random number generator.



endmenu



config ARM64_SVE

	bool "ARM Scalable Vector Extension support"

	default y

arch/arm64/include/asm/archrandom.h

0 → 100644
+67 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_ARCHRANDOM_H

#define _ASM_ARCHRANDOM_H



#ifdef CONFIG_ARCH_RANDOM



#include <linux/random.h>

#include <asm/cpufeature.h>



static inline bool __arm64_rndr(unsigned long *v)

{

	bool ok;



	/*

	 * Reads of RNDR set PSTATE.NZCV to 0b0000 on success,

	 * and set PSTATE.NZCV to 0b0100 otherwise.

	 */

	asm volatile(

		__mrs_s("%0", SYS_RNDR_EL0) "\n"

	"	cset %w1, ne\n"

	: "=r" (*v), "=r" (ok)

	:

	: "cc");



	return ok;

}



static inline bool __must_check arch_get_random_long(unsigned long *v)

{

	return false;

}



static inline bool __must_check arch_get_random_int(unsigned int *v)

{

	return false;

}



static inline bool __must_check arch_get_random_seed_long(unsigned long *v)

{

	/*

	 * Only support the generic interface after we have detected

	 * the system wide capability, avoiding complexity with the

	 * cpufeature code and with potential scheduling between CPUs

	 * with and without the feature.

	 */

	if (!cpus_have_const_cap(ARM64_HAS_RNG))

		return false;



	return __arm64_rndr(v);

}





static inline bool __must_check arch_get_random_seed_int(unsigned int *v)

{

	unsigned long val;

	bool ok = arch_get_random_seed_long(&val);



	*v = val;

	return ok;

}



#else



static inline bool __arm64_rndr(unsigned long *v) { return false; }



#endif /* CONFIG_ARCH_RANDOM */

#endif /* _ASM_ARCHRANDOM_H */

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -56,7 +56,8 @@ 
#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM	46

#define ARM64_WORKAROUND_1542419		47

#define ARM64_WORKAROUND_1319367		48

#define ARM64_HAS_RNG				49



#define ARM64_NCAPS				49

#define ARM64_NCAPS				50



#endif /* __ASM_CPUCAPS_H */

CRA Git | Maintained and supported by SUSTech CRA and CCSE