Commit 1a472c9d authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
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powerpc/mm/radix: Add tlbflush routines 



Core kernel doesn't track the page size of the VA range that we are
invalidating. Hence we end up flushing TLB for the entire mm here. Later
patches will improve this.

We also don't flush page walk cache separetly instead use RIC=2 when
flushing TLB, because we do a MMU gather flush after freeing page table.

MMU_NO_CONTEXT is updated for hash.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 676012a6

arch/powerpc/include/asm/book3s/64/mmu-hash.h

+1 −0
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ 
#define POWER7_TLB_SETS		128	/* # sets in POWER7 TLB */

#define POWER8_TLB_SETS		512	/* # sets in POWER8 TLB */

#define POWER9_TLB_SETS_HASH	256	/* # sets in POWER9 TLB Hash mode */

#define POWER9_TLB_SETS_RADIX	128	/* # sets in POWER9 TLB Radix mode */



#ifndef __ASSEMBLY__

arch/powerpc/include/asm/book3s/64/tlbflush-hash.h

+9 −4
Original line number Diff line number Diff line 
#ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H

#define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H



#define MMU_NO_CONTEXT		0



/*

 * TLB flushing for 64-bit hash-MMU CPUs

 */
@@ -29,14 +27,21 @@ extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch); 


static inline void arch_enter_lazy_mmu_mode(void)

{

	struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);

	struct ppc64_tlb_batch *batch;



	if (radix_enabled())

		return;

	batch = this_cpu_ptr(&ppc64_tlb_batch);

	batch->active = 1;

}



static inline void arch_leave_lazy_mmu_mode(void)

{

	struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);

	struct ppc64_tlb_batch *batch;



	if (radix_enabled())

		return;

	batch = this_cpu_ptr(&ppc64_tlb_batch);



	if (batch->index)

		__flush_tlb_pending(batch);

arch/powerpc/include/asm/book3s/64/tlbflush-radix.h

0 → 100644
+33 −0
Original line number Diff line number Diff line 
#ifndef _ASM_POWERPC_TLBFLUSH_RADIX_H

#define _ASM_POWERPC_TLBFLUSH_RADIX_H



struct vm_area_struct;

struct mm_struct;

struct mmu_gather;



static inline int mmu_get_ap(int psize)

{

	return mmu_psize_defs[psize].ap;

}



extern void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,

			    unsigned long end);

extern void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end);



extern void radix__local_flush_tlb_mm(struct mm_struct *mm);

extern void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);

extern void radix___local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,

				    unsigned long ap, int nid);

extern void radix__tlb_flush(struct mmu_gather *tlb);

#ifdef CONFIG_SMP

extern void radix__flush_tlb_mm(struct mm_struct *mm);

extern void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);

extern void radix___flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,

			      unsigned long ap, int nid);

#else

#define radix__flush_tlb_mm(mm)		radix__local_flush_tlb_mm(mm)

#define radix__flush_tlb_page(vma,addr)	radix__local_flush_tlb_page(vma,addr)

#define radix___flush_tlb_page(mm,addr,p,i)	radix___local_flush_tlb_page(mm,addr,p,i)

#endif



#endif

arch/powerpc/include/asm/book3s/64/tlbflush.h

+20 −0
Original line number Diff line number Diff line 
#ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_H

#define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_H



#define MMU_NO_CONTEXT	~0UL





#include <asm/book3s/64/tlbflush-hash.h>

#include <asm/book3s/64/tlbflush-radix.h>



static inline void flush_tlb_range(struct vm_area_struct *vma,

				   unsigned long start, unsigned long end)

{

	if (radix_enabled())

		return radix__flush_tlb_range(vma, start, end);

	return hash__flush_tlb_range(vma, start, end);

}



static inline void flush_tlb_kernel_range(unsigned long start,

					  unsigned long end)

{

	if (radix_enabled())

		return radix__flush_tlb_kernel_range(start, end);

	return hash__flush_tlb_kernel_range(start, end);

}



static inline void local_flush_tlb_mm(struct mm_struct *mm)

{

	if (radix_enabled())

		return radix__local_flush_tlb_mm(mm);

	return hash__local_flush_tlb_mm(mm);

}



static inline void local_flush_tlb_page(struct vm_area_struct *vma,

					unsigned long vmaddr)

{

	if (radix_enabled())

		return radix__local_flush_tlb_page(vma, vmaddr);

	return hash__local_flush_tlb_page(vma, vmaddr);

}



static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,

					 unsigned long vmaddr)

{

	if (radix_enabled())

		return radix__flush_tlb_page(vma, vmaddr);

	return hash__flush_tlb_page_nohash(vma, vmaddr);

}



static inline void tlb_flush(struct mmu_gather *tlb)

{

	if (radix_enabled())

		return radix__tlb_flush(tlb);

	return hash__tlb_flush(tlb);

}



#ifdef CONFIG_SMP

static inline void flush_tlb_mm(struct mm_struct *mm)

{

	if (radix_enabled())

		return radix__flush_tlb_mm(mm);

	return hash__flush_tlb_mm(mm);

}



static inline void flush_tlb_page(struct vm_area_struct *vma,

				  unsigned long vmaddr)

{

	if (radix_enabled())

		return radix__flush_tlb_page(vma, vmaddr);

	return hash__flush_tlb_page(vma, vmaddr);

}

#else

arch/powerpc/include/asm/tlbflush.h

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ extern void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, 


#elif defined(CONFIG_PPC_STD_MMU_32)



#define MMU_NO_CONTEXT      (0)

/*

 * TLB flushing for "classic" hash-MMU 32-bit CPUs, 6xx, 7xx, 7xxx

 */

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