Commit 1a31c26e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'du-next-20181123' of git://linuxtv.org/pinchartl/media into drm-next 



R-Car DU changes for v4.21:

- R8A7744 and R8A77470 support
- R8A77965 LVDS support
- Miscellaneous fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3165107.GPE8tO0qUE@avalon
parents bfeb122d 256856ef

Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ Required properties: 
  - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders

  - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders

  - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders

  - "renesas,r8a77965-lvds" for R8A77965 (R-Car M3-N) compatible LVDS encoders

  - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders

  - "renesas,r8a77980-lvds" for R8A77980 (R-Car V3H) compatible LVDS encoders

  - "renesas,r8a77990-lvds" for R8A77990 (R-Car E3) compatible LVDS encoders

Documentation/devicetree/bindings/display/renesas,du.txt

+4 −0
Original line number Diff line number Diff line
@@ -4,7 +4,9 @@ Required Properties: 


  - compatible: must be one of the following.

    - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU

    - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU

    - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU

    - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU

    - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU

    - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU

    - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
@@ -52,7 +54,9 @@ corresponding to each DU output. 
                        Port0          Port1          Port2          Port3

-----------------------------------------------------------------------------

 R8A7743 (RZ/G1M)       DPAD 0         LVDS 0         -              -

 R8A7744 (RZ/G1N)       DPAD 0         LVDS 0         -              -

 R8A7745 (RZ/G1E)       DPAD 0         DPAD 1         -              -

 R8A77470 (RZ/G1C)      DPAD 0         DPAD 1         LVDS 0         -

 R8A7779 (R-Car H1)     DPAD 0         DPAD 1         -              -

 R8A7790 (R-Car H2)     DPAD 0         LVDS 0         LVDS 1         -

 R8A7791 (R-Car M2-W)   DPAD 0         LVDS 0         -              -

drivers/gpu/drm/rcar-du/rcar_du_crtc.c

+23 −7
Original line number Diff line number Diff line
@@ -226,9 +226,6 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) 
		 * system clock, and have no internal clock divider.

		 */



		if (WARN_ON(!rcrtc->extclock))

			return;



		/*

		 * The H3 ES1.x exhibits dot clock duty cycle stability issues.

		 * We can work around them by configuring the DPLL to twice the
@@ -701,7 +698,7 @@ static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc, 
	 * CRTC will be put later in .atomic_disable().

	 *

	 * If a mode set is not in progress the CRTC is enabled, and the

	 * following get call will be a no-op. There is thus no need to belance

	 * following get call will be a no-op. There is thus no need to balance

	 * it in .atomic_flush() either.

	 */

	rcar_du_crtc_get(rcrtc);
@@ -738,10 +735,22 @@ enum drm_mode_status rcar_du_crtc_mode_valid(struct drm_crtc *crtc, 
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);

	struct rcar_du_device *rcdu = rcrtc->group->dev;

	bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;

	unsigned int vbp;



	if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))

		return MODE_NO_INTERLACE;



	/*

	 * The hardware requires a minimum combined horizontal sync and back

	 * porch of 20 pixels and a minimum vertical back porch of 3 lines.

	 */

	if (mode->htotal - mode->hsync_start < 20)

		return MODE_HBLANK_NARROW;



	vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1);

	if (vbp < 3)

		return MODE_VBLANK_NARROW;



	return MODE_OK;

}
@@ -1002,7 +1011,7 @@ unlock: 
	drm_modeset_drop_locks(&ctx);

	drm_modeset_acquire_fini(&ctx);



	return 0;

	return ret;

}



static const struct drm_crtc_funcs crtc_funcs_gen2 = {
@@ -1113,9 +1122,16 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, 
	clk = devm_clk_get(rcdu->dev, clk_name);

	if (!IS_ERR(clk)) {

		rcrtc->extclock = clk;

	} else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {

		dev_info(rcdu->dev, "can't get external clock %u\n", hwindex);

	} else if (PTR_ERR(clk) == -EPROBE_DEFER) {

		return -EPROBE_DEFER;

	} else if (rcdu->info->dpll_mask & BIT(hwindex)) {

		/*

		 * DU channels that have a display PLL can't use the internal

		 * system clock and thus require an external clock.

		 */

		ret = PTR_ERR(clk);

		dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret);

		return ret;

	}



	init_waitqueue_head(&rcrtc->flip_wait);

drivers/gpu/drm/rcar-du/rcar_du_drv.c

+31 −2
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = { 
	.channels_mask = BIT(1) | BIT(0),

	.routes = {

		/*

		 * R8A7743 has one RGB output and one LVDS output

		 * R8A774[34] has one RGB output and one LVDS output

		 */

		[RCAR_DU_OUTPUT_DPAD0] = {

			.possible_crtcs = BIT(1) | BIT(0),
@@ -77,6 +77,33 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = { 
	},

};



static const struct rcar_du_device_info rzg1_du_r8a77470_info = {

	.gen = 2,

	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK

		  | RCAR_DU_FEATURE_EXT_CTRL_REGS

		  | RCAR_DU_FEATURE_INTERLACED

		  | RCAR_DU_FEATURE_TVM_SYNC,

	.channels_mask = BIT(1) | BIT(0),

	.routes = {

		/*

		 * R8A77470 has two RGB outputs, one LVDS output, and

		 * one (currently unsupported) analog video output

		 */

		[RCAR_DU_OUTPUT_DPAD0] = {

			.possible_crtcs = BIT(0),

			.port = 0,

		},

		[RCAR_DU_OUTPUT_DPAD1] = {

			.possible_crtcs = BIT(1),

			.port = 1,

		},

		[RCAR_DU_OUTPUT_LVDS0] = {

			.possible_crtcs = BIT(0) | BIT(1),

			.port = 2,

		},

	},

};



static const struct rcar_du_device_info rcar_du_r8a7779_info = {

	.gen = 2,

	.features = RCAR_DU_FEATURE_INTERLACED
@@ -341,7 +368,9 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = { 


static const struct of_device_id rcar_du_of_table[] = {

	{ .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },

	{ .compatible = "renesas,du-r8a7744", .data = &rzg1_du_r8a7743_info },

	{ .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },

	{ .compatible = "renesas,du-r8a77470", .data = &rzg1_du_r8a77470_info },

	{ .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },

	{ .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },

	{ .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
@@ -437,7 +466,7 @@ static int rcar_du_remove(struct platform_device *pdev) 
	drm_kms_helper_poll_fini(ddev);

	drm_mode_config_cleanup(ddev);



	drm_dev_unref(ddev);

	drm_dev_put(ddev);



	return 0;

}

drivers/gpu/drm/rcar-du/rcar_du_kms.c

+1 −1
Original line number Diff line number Diff line
@@ -582,7 +582,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu) 
	 * Initialize vertical blanking interrupts handling. Start with vblank

	 * disabled for all CRTCs.

	 */

	ret = drm_vblank_init(dev, (1 << rcdu->num_crtcs) - 1);

	ret = drm_vblank_init(dev, rcdu->num_crtcs);

	if (ret < 0)

		return ret;

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