Commit 1a1c7821 authored by Taniya Das's avatar Taniya Das Committed by Stephen Boyd
Browse files

clk: qcom: rcg: update the DFS macro for RCG 



Update the init data name for each of the dynamic frequency switch
controlled clock associated with the RCG clock name, so that it can be
generated as per the hardware plan. Thus update the macro accordingly.

Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20191014102308.27441-2-tdas@codeaurora.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 57b2364d

drivers/clk/qcom/clk-rcg.h

+1 −1
Original line number Diff line number Diff line
@@ -168,7 +168,7 @@ struct clk_rcg_dfs_data { 
};



#define DEFINE_RCG_DFS(r) \

	{ .rcg = &r##_src, .init = &r##_init }

	{ .rcg = &r, .init = &r##_init }



extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,

				    const struct clk_rcg_dfs_data *rcgs,

drivers/clk/qcom/gcc-sdm845.c

+48 −48
Original line number Diff line number Diff line
@@ -408,7 +408,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 
	{ }

};



static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {

static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {

	.name = "gcc_qupv3_wrap0_s0_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -421,10 +421,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = {

static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {

	.name = "gcc_qupv3_wrap0_s1_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -437,10 +437,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = {

static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {

	.name = "gcc_qupv3_wrap0_s2_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -453,10 +453,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = {

static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {

	.name = "gcc_qupv3_wrap0_s3_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -469,10 +469,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = {

static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {

	.name = "gcc_qupv3_wrap0_s4_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -485,10 +485,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = {

static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {

	.name = "gcc_qupv3_wrap0_s5_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -501,10 +501,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = {

static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {

	.name = "gcc_qupv3_wrap0_s6_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -517,10 +517,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = {

static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {

	.name = "gcc_qupv3_wrap0_s7_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -533,10 +533,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = {

static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {

	.name = "gcc_qupv3_wrap1_s0_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -549,10 +549,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = {

static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {

	.name = "gcc_qupv3_wrap1_s1_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -565,10 +565,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = {

static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {

	.name = "gcc_qupv3_wrap1_s2_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -581,10 +581,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = {

static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {

	.name = "gcc_qupv3_wrap1_s3_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -597,10 +597,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = {

static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {

	.name = "gcc_qupv3_wrap1_s4_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -613,10 +613,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = {

static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {

	.name = "gcc_qupv3_wrap1_s5_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -629,10 +629,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = {

static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {

	.name = "gcc_qupv3_wrap1_s6_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -645,10 +645,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,

};



static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = {

static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {

	.name = "gcc_qupv3_wrap1_s7_clk_src",

	.parent_names = gcc_parent_names_0,

	.num_parents = 4,
@@ -661,7 +661,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 
	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,

	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init,

	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,

};



static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
@@ -3577,22 +3577,22 @@ static const struct of_device_id gcc_sdm845_match_table[] = { 
MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);



static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),

	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),

};



static int gcc_sdm845_probe(struct platform_device *pdev)

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