Commit 1a0c4ca5 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v4.10-next-dts32' of https://github.com/mbgg/linux-mediatek into next/dt 

Lots of updates for mt2701:
Rearrange the dt nodes and fix unit address for pincontroler
Add nodes for:
- clock controller subsystems
- scpsys controller
- iommu and smi
- spi
- nand
- auxadc
- thermal controller and zones

Email address updated for mt7623 devicetree files.

* tag 'v4.10-next-dts32' of https://github.com/mbgg/linux-mediatek

:
  arm: dts: mt2701: Add thermal device node.
  arm: dts: mt2701: Add auxadc device node.
  arm: dts: mt2701: Add nand device node
  arm: dts: mt2701: Add spi device node
  ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
  ARM: dts: mediatek: update my email address
  arm: dts: mt2701: Add power domain controller device node
  arm: dts: mt2701: Add subsystem clock controller device nodes
  arm: dts: mt2701: Sort DT nodes by register address

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 7a38003b e348dc74

arch/arm/boot/dts/mt2701-evb.dts

+54 −0
Original line number Diff line number Diff line
@@ -24,6 +24,60 @@ 
	};

};



&auxadc {

	status = "okay";

};



&pio {

	spi_pins_a: spi0@0 {

		pins_spi {

			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,

				 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,

				 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,

				 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;

			bias-disable;

		};

	};



	spi_pins_b: spi1@0 {

		pins_spi {

			pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,

				 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,

				 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,

				 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;

			bias-disable;

		};

	};



	spi_pins_c: spi2@0 {

		pins_spi {

			pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,

				 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,

				 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,

				 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;

			bias-disable;

		};

	};

};



&spi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_a>;

	status = "disabled";

};



&spi1 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_b>;

	status = "disabled";

};



&spi2 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_c>;

	status = "disabled";

};



&uart0 {

	status = "okay";

};

arch/arm/boot/dts/mt2701.dtsi

+229 −18
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
 */



#include <dt-bindings/clock/mt2701-clk.h>

#include <dt-bindings/power/mt2701-power.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/reset/mt2701-resets.h>
@@ -87,6 +88,36 @@ 
		clock-output-names = "rtc32k";

	};



	thermal-zones {

		cpu_thermal: cpu_thermal {

			polling-delay-passive = <1000>; /* milliseconds */

			polling-delay = <1000>; /* milliseconds */



			thermal-sensors = <&thermal 0>;

			sustainable-power = <1000>;



			trips {

				threshold: trip-point@0 {

					temperature = <68000>;

					hysteresis = <2000>;

					type = "passive";

				};



				target: trip-point@1 {

					temperature = <85000>;

					hysteresis = <2000>;

					type = "passive";

				};



				cpu_crit: cpu_crit@0 {

					temperature = <115000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};

		};

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupt-parent = <&gic>;
@@ -96,24 +127,6 @@ 
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

	};



	pio: pinctrl@10005000 {

		compatible = "mediatek,mt2701-pinctrl";

		reg = <0 0x1000b000 0 0x1000>;

		mediatek,pctl-regmap = <&syscfg_pctl_a>;

		pins-are-numbered;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

	};



	syscfg_pctl_a: syscfg@10005000 {

		compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";

		reg = <0 0x10005000 0 0x1000>;

	};



	topckgen: syscon@10000000 {

		compatible = "mediatek,mt2701-topckgen", "syscon";

		reg = <0 0x10000000 0 0x1000>;
@@ -134,6 +147,22 @@ 
		#reset-cells = <1>;

	};



	syscfg_pctl_a: syscfg@10005000 {

		compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";

		reg = <0 0x10005000 0 0x1000>;

	};



	scpsys: scpsys@10006000 {

		compatible = "mediatek,mt2701-scpsys", "syscon";

		#power-domain-cells = <1>;

		reg = <0 0x10006000 0 0x1000>;

		infracfg = <&infracfg>;

		clocks = <&topckgen CLK_TOP_MM_SEL>,

			 <&topckgen CLK_TOP_MFG_SEL>,

			 <&topckgen CLK_TOP_ETHIF_SEL>;

		clock-names = "mm", "mfg", "ethif";

	};



	watchdog: watchdog@10007000 {

		compatible = "mediatek,mt2701-wdt",

			     "mediatek,mt6589-wdt";
@@ -149,6 +178,29 @@ 
		clock-names = "system-clk", "rtc-clk";

	};



	pio: pinctrl@1000b000 {

		compatible = "mediatek,mt2701-pinctrl";

		reg = <0 0x1000b000 0 0x1000>;

		mediatek,pctl-regmap = <&syscfg_pctl_a>;

		pins-are-numbered;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

	};



	smi_common: smi@1000c000 {

		compatible = "mediatek,mt2701-smi-common";

		reg = <0 0x1000c000 0 0x1000>;

		clocks = <&infracfg CLK_INFRA_SMI>,

			 <&mmsys CLK_MM_SMI_COMMON>,

			 <&infracfg CLK_INFRA_SMI>;

		clock-names = "apb", "smi", "async";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};



	sysirq: interrupt-controller@10200100 {

		compatible = "mediatek,mt2701-sysirq",

			     "mediatek,mt6577-sysirq";
@@ -158,6 +210,16 @@ 
		reg = <0 0x10200100 0 0x1c>;

	};



	iommu: mmsys_iommu@10205000 {

		compatible = "mediatek,mt2701-m4u";

		reg = <0 0x10205000 0 0x1000>;

		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_M4U>;

		clock-names = "bclk";

		mediatek,larbs = <&larb0 &larb1 &larb2>;

		#iommu-cells = <1>;

	};



	apmixedsys: syscon@10209000 {

		compatible = "mediatek,mt2701-apmixedsys", "syscon";

		reg = <0 0x10209000 0 0x1000>;
@@ -175,6 +237,15 @@ 
		      <0 0x10216000 0 0x2000>;

	};



	auxadc: adc@11001000 {

		compatible = "mediatek,mt2701-auxadc";

		reg = <0 0x11001000 0 0x1000>;

		clocks = <&pericfg CLK_PERI_AUXADC>;

		clock-names = "main";

		#io-channel-cells = <1>;

		status = "disabled";

	};



	uart0: serial@11002000 {

		compatible = "mediatek,mt2701-uart",

			     "mediatek,mt6577-uart";
@@ -214,4 +285,144 @@ 
		clock-names = "baud", "bus";

		status = "disabled";

	};



	spi0: spi@1100a000 {

		compatible = "mediatek,mt2701-spi";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0 0x1100a000 0 0x100>;

		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,

			 <&topckgen CLK_TOP_SPI0_SEL>,

			 <&pericfg CLK_PERI_SPI0>;

		clock-names = "parent-clk", "sel-clk", "spi-clk";

		status = "disabled";

	};



	thermal: thermal@1100b000 {

		#thermal-sensor-cells = <0>;

		compatible = "mediatek,mt2701-thermal";

		reg = <0 0x1100b000 0 0x1000>;

		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;

		clock-names = "therm", "auxadc";

		resets = <&pericfg MT2701_PERI_THERM_SW_RST>;

		reset-names = "therm";

		mediatek,auxadc = <&auxadc>;

		mediatek,apmixedsys = <&apmixedsys>;

	};



	nandc: nfi@1100d000 {

		compatible = "mediatek,mt2701-nfc";

		reg = <0 0x1100d000 0 0x1000>;

		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&pericfg CLK_PERI_NFI>,

			 <&pericfg CLK_PERI_NFI_PAD>;

		clock-names = "nfi_clk", "pad_clk";

		status = "disabled";

		ecc-engine = <&bch>;

		#address-cells = <1>;

		#size-cells = <0>;

	};



	bch: ecc@1100e000 {

		compatible = "mediatek,mt2701-ecc";

		reg = <0 0x1100e000 0 0x1000>;

		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&pericfg CLK_PERI_NFI_ECC>;

		clock-names = "nfiecc_clk";

		status = "disabled";

	};



	spi1: spi@11016000 {

		compatible = "mediatek,mt2701-spi";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0 0x11016000 0 0x100>;

		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,

			 <&topckgen CLK_TOP_SPI1_SEL>,

			 <&pericfg CLK_PERI_SPI1>;

		clock-names = "parent-clk", "sel-clk", "spi-clk";

		status = "disabled";

	};



	spi2: spi@11017000 {

		compatible = "mediatek,mt2701-spi";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0 0x11017000 0 0x1000>;

		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,

			 <&topckgen CLK_TOP_SPI2_SEL>,

			 <&pericfg CLK_PERI_SPI2>;

		clock-names = "parent-clk", "sel-clk", "spi-clk";

		status = "disabled";

	};



	mmsys: syscon@14000000 {

		compatible = "mediatek,mt2701-mmsys", "syscon";

		reg = <0 0x14000000 0 0x1000>;

		#clock-cells = <1>;

	};



	larb0: larb@14010000 {

		compatible = "mediatek,mt2701-smi-larb";

		reg = <0 0x14010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		clocks = <&mmsys CLK_MM_SMI_LARB0>,

			 <&mmsys CLK_MM_SMI_LARB0>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};



	imgsys: syscon@15000000 {

		compatible = "mediatek,mt2701-imgsys", "syscon";

		reg = <0 0x15000000 0 0x1000>;

		#clock-cells = <1>;

	};



	larb2: larb@15001000 {

		compatible = "mediatek,mt2701-smi-larb";

		reg = <0 0x15001000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		clocks = <&imgsys CLK_IMG_SMI_COMM>,

			 <&imgsys CLK_IMG_SMI_COMM>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

	};



	vdecsys: syscon@16000000 {

		compatible = "mediatek,mt2701-vdecsys", "syscon";

		reg = <0 0x16000000 0 0x1000>;

		#clock-cells = <1>;

	};



	larb1: larb@16010000 {

		compatible = "mediatek,mt2701-smi-larb";

		reg = <0 0x16010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		clocks = <&vdecsys CLK_VDEC_CKGEN>,

			 <&vdecsys CLK_VDEC_LARB>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;

	};



	hifsys: syscon@1a000000 {

		compatible = "mediatek,mt2701-hifsys", "syscon";

		reg = <0 0x1a000000 0 0x1000>;

		#clock-cells = <1>;

	};



	ethsys: syscon@1b000000 {

		compatible = "mediatek,mt2701-ethsys", "syscon";

		reg = <0 0x1b000000 0 0x1000>;

		#clock-cells = <1>;

	};



	bdpsys: syscon@1c000000 {

		compatible = "mediatek,mt2701-bdpsys", "syscon";

		reg = <0 0x1c000000 0 0x1000>;

		#clock-cells = <1>;

	};

};

arch/arm/boot/dts/mt7623-evb.dts

+1 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016 MediaTek Inc.

 * Author: John Crispin <blogic@openwrt.org>

 * Author: John Crispin <john@phrozen.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

arch/arm/boot/dts/mt7623.dtsi

+1 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016 MediaTek Inc.

 * Author: John Crispin <blogic@openwrt.org>

 * Author: John Crispin <john@phrozen.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

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