Commit 19fe87fd authored by Akshu Agrawal's avatar Akshu Agrawal Committed by Rafael J. Wysocki
Browse files

clk: x86: Support RV architecture 



There is minor difference between previous family of SoC and
the current one. Which is the there is only 48Mh fixed clk.
There is no mux and no option to select another freq as there in previous.

Signed-off-by: default avatarAkshu Agrawal <akshu.agrawal@amd.com>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 7f8802f2

drivers/clk/x86/clk-fch.c

+38 −15
Original line number Diff line number Diff line
@@ -26,6 +26,10 @@ 
#define ST_CLK_GATE	3

#define ST_MAX_CLKS	4



#define RV_CLK_48M	0

#define RV_CLK_GATE	1

#define RV_MAX_CLKS	2



static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };

static struct clk_hw *hws[ST_MAX_CLKS];
@@ -37,33 +41,52 @@ static int fch_clk_probe(struct platform_device *pdev) 
	if (!fch_data || !fch_data->base)

		return -EINVAL;



	hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,

						     48000000);

	hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,

						     25000000);

	if (!fch_data->is_rv) {

		hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",

			NULL, 0, 48000000);

		hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",

			NULL, 0, 25000000);



		hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",

			clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),

		0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);

			0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0,

			NULL);



		clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);



	hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",

		0, fch_data->base + MISCCLKCNTL1, OSCCLKENB,

		CLK_GATE_SET_TO_DISABLE, NULL);

		hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",

			"oscout1_mux", 0, fch_data->base + MISCCLKCNTL1,

			OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);



	devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], "oscout1",

				    NULL);

		devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE],

			"oscout1", NULL);

	} else {

		hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",

			NULL, 0, 48000000);



		hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",

			"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,

			OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);



		devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE],

			"oscout1", NULL);

	}



	return 0;

}



static int fch_clk_remove(struct platform_device *pdev)

{

	int i;

	int i, clks;

	struct fch_clk_data *fch_data;



	fch_data = dev_get_platdata(&pdev->dev);



	for (i = 0; i < ST_MAX_CLKS; i++)

	clks = fch_data->is_rv ? RV_MAX_CLKS : ST_MAX_CLKS;



	for (i = 0; i < clks; i++)

		clk_hw_unregister(hws[i]);



	return 0;

}

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