Commit 19edeb38 authored by Pankaj Bharadiya's avatar Pankaj Bharadiya Committed by Jani Nikula
Browse files

drm/i915/pm: Prefer drm_WARN_ON over WARN_ON 



struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.

Prefer drm_WARN_ON over WARN_ON.

Conversion is done with below sementic patch:

@@
identifier func, T;
@@
func(...) {
...
struct intel_crtc *T = ...;
+struct drm_i915_private *dev_priv = to_i915(T->base.dev);
<+...
-WARN_ON(
+drm_WARN_ON(&dev_priv->drm,
...)
...+>

}

@@
identifier func, T;
@@
func(struct intel_crtc_state *T,...) {
+struct drm_i915_private *dev_priv = to_i915(T->uapi.crtc->dev);
<+...
-WARN_ON(
+drm_WARN_ON(&dev_priv->drm,
...)
...+>

}

changes since v1:
    - Added dev_priv local variable and used it in drm_WARN_ON calls (Jani)

Signed-off-by: default avatarPankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200504181600.18503-9-pankaj.laxminarayan.bharadiya@intel.com
parent bf07f6eb

drivers/gpu/drm/i915/intel_pm.c

+38 −25
Original line number Diff line number Diff line
@@ -1437,6 +1437,7 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) 
static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;

	const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;

	struct intel_atomic_state *intel_state =
@@ -1465,7 +1466,7 @@ static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state) 
			max(optimal->wm.plane[plane_id],

			    active->wm.plane[plane_id]);



		WARN_ON(intermediate->wm.plane[plane_id] >

		drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] >

			    g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));

	}
@@ -1483,20 +1484,24 @@ static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state) 
	intermediate->hpll.fbc = max(optimal->hpll.fbc,

				     active->hpll.fbc);



	WARN_ON((intermediate->sr.plane >

	drm_WARN_ON(&dev_priv->drm,

		    (intermediate->sr.plane >

		     g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||

		     intermediate->sr.cursor >

		     g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&

		    intermediate->cxsr);

	WARN_ON((intermediate->sr.plane >

	drm_WARN_ON(&dev_priv->drm,

		    (intermediate->sr.plane >

		     g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||

		     intermediate->sr.cursor >

		     g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&

		    intermediate->hpll_en);



	WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&

	drm_WARN_ON(&dev_priv->drm,

		    intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&

		    intermediate->fbc_en && intermediate->cxsr);

	WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&

	drm_WARN_ON(&dev_priv->drm,

		    intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&

		    intermediate->fbc_en && intermediate->hpll_en);



out:
@@ -1681,6 +1686,7 @@ static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes) 
static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	const struct g4x_pipe_wm *raw =

		&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];

	struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
@@ -1749,11 +1755,11 @@ static int vlv_compute_fifo(struct intel_crtc_state *crtc_state) 
		fifo_left -= plane_extra;

	}



	WARN_ON(active_planes != 0 && fifo_left != 0);

	drm_WARN_ON(&dev_priv->drm, active_planes != 0 && fifo_left != 0);



	/* give it all to the first plane if none are active */

	if (active_planes == 0) {

		WARN_ON(fifo_left != fifo_size);

		drm_WARN_ON(&dev_priv->drm, fifo_left != fifo_size);

		fifo_state->plane[PLANE_PRIMARY] = fifo_left;

	}
@@ -4333,11 +4339,13 @@ static uint_fixed_16_16_t 
skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,

			   const struct intel_plane_state *plane_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	u32 src_w, src_h, dst_w, dst_h;

	uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;

	uint_fixed_16_16_t downscale_h, downscale_w;



	if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))

	if (drm_WARN_ON(&dev_priv->drm,

			!intel_wm_plane_visible(crtc_state, plane_state)))

		return u32_to_fixed16(0);



	/*
@@ -5031,6 +5039,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency, 
static uint_fixed_16_16_t

intel_get_linetime_us(const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	u32 pixel_rate;

	u32 crtc_htotal;

	uint_fixed_16_16_t linetime_us;
@@ -5040,7 +5049,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state) 


	pixel_rate = crtc_state->pixel_rate;



	if (WARN_ON(pixel_rate == 0))

	if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))

		return u32_to_fixed16(0);



	crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
@@ -5053,11 +5062,13 @@ static u32 
skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,

			      const struct intel_plane_state *plane_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	u64 adjusted_pixel_rate;

	uint_fixed_16_16_t downscale_amount;



	/* Shouldn't reach here on disabled planes... */

	if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))

	if (drm_WARN_ON(&dev_priv->drm,

			!intel_wm_plane_visible(crtc_state, plane_state)))

		return 0;



	/*
@@ -5493,6 +5504,7 @@ static int skl_build_plane_wm(struct intel_crtc_state *crtc_state, 
static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,

			      const struct intel_plane_state *plane_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	enum plane_id plane_id = to_intel_plane(plane_state->uapi.plane)->id;

	int ret;
@@ -5504,8 +5516,9 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, 
		const struct drm_framebuffer *fb = plane_state->hw.fb;

		enum plane_id y_plane_id = plane_state->planar_linked_plane->id;



		WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state));

		WARN_ON(!fb->format->is_yuv ||

		drm_WARN_ON(&dev_priv->drm,

			    !intel_wm_plane_visible(crtc_state, plane_state));

		drm_WARN_ON(&dev_priv->drm, !fb->format->is_yuv ||

			    fb->format->num_planes == 1);



		ret = skl_build_plane_wm_single(crtc_state, plane_state,

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