Commit 19d28fbd authored by David S. Miller's avatar David S. Miller
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 



BPF alignment tests got a conflict because the registers
are output as Rn_w instead of just Rn in net-next, and
in net a fixup for a testcase prohibits logical operations
on pointers before using them.

Also, we should attempt to patch BPF call args if JIT always on is
enabled.  Instead, if we fail to JIT the subprogs we should pass
an error back up and fail immediately.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 8c2e6c90 1545dec4

Documentation/networking/index.rst

+1 −1
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Contents: 
   batman-adv

   kapi

   z8530book

   msg_zerocopy



.. only::  subproject
@@ -16,4 +17,3 @@ Contents: 
   =======



   * :ref:`genindex`

Documentation/networking/msg_zerocopy.rst

+4 −0
Original line number Diff line number Diff line
@@ -72,6 +72,10 @@ this flag, a process must first signal intent by setting a socket option: 
	if (setsockopt(fd, SOL_SOCKET, SO_ZEROCOPY, &one, sizeof(one)))

		error(1, errno, "setsockopt zerocopy");



Setting the socket option only works when the socket is in its initial

(TCP_CLOSED) state.  Trying to set the option for a socket returned by accept(),

for example, will lead to an EBUSY error. In this case, the option should be set

to the listening socket and it will be inherited by the accepted sockets.



Transmission

------------

arch/mips/kernel/cps-vec.S

+2 −0
Original line number Diff line number Diff line
@@ -235,6 +235,7 @@ LEAF(mips_cps_core_init) 
	has_mt	t0, 3f



	.set	push

	.set	MIPS_ISA_LEVEL_RAW

	.set	mt



	/* Only allow 1 TC per VPE to execute... */
@@ -388,6 +389,7 @@ LEAF(mips_cps_boot_vpes) 
#elif defined(CONFIG_MIPS_MT)



	.set	push

	.set	MIPS_ISA_LEVEL_RAW

	.set	mt



	/* If the core doesn't support MT then return */

arch/mips/kernel/process.c

+12 −0
Original line number Diff line number Diff line
@@ -705,6 +705,18 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) 
	struct task_struct *t;

	int max_users;



	/* If nothing to change, return right away, successfully.  */

	if (value == mips_get_process_fp_mode(task))

		return 0;



	/* Only accept a mode change if 64-bit FP enabled for o32.  */

	if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))

		return -EOPNOTSUPP;



	/* And only for o32 tasks.  */

	if (IS_ENABLED(CONFIG_64BIT) && !test_thread_flag(TIF_32BIT_REGS))

		return -EOPNOTSUPP;



	/* Check the value is valid */

	if (value & ~known_bits)

		return -EOPNOTSUPP;

arch/mips/kernel/ptrace.c

+122 −25
Original line number Diff line number Diff line
@@ -419,63 +419,160 @@ static int gpr64_set(struct task_struct *target, 


#endif /* CONFIG_64BIT */



/*

 * Copy the floating-point context to the supplied NT_PRFPREG buffer,

 * !CONFIG_CPU_HAS_MSA variant.  FP context's general register slots

 * correspond 1:1 to buffer slots.  Only general registers are copied.

 */

static int fpr_get_fpa(struct task_struct *target,

		       unsigned int *pos, unsigned int *count,

		       void **kbuf, void __user **ubuf)

{

	return user_regset_copyout(pos, count, kbuf, ubuf,

				   &target->thread.fpu,

				   0, NUM_FPU_REGS * sizeof(elf_fpreg_t));

}



/*

 * Copy the floating-point context to the supplied NT_PRFPREG buffer,

 * CONFIG_CPU_HAS_MSA variant.  Only lower 64 bits of FP context's

 * general register slots are copied to buffer slots.  Only general

 * registers are copied.

 */

static int fpr_get_msa(struct task_struct *target,

		       unsigned int *pos, unsigned int *count,

		       void **kbuf, void __user **ubuf)

{

	unsigned int i;

	u64 fpr_val;

	int err;



	BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t));

	for (i = 0; i < NUM_FPU_REGS; i++) {

		fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0);

		err = user_regset_copyout(pos, count, kbuf, ubuf,

					  &fpr_val, i * sizeof(elf_fpreg_t),

					  (i + 1) * sizeof(elf_fpreg_t));

		if (err)

			return err;

	}



	return 0;

}



/*

 * Copy the floating-point context to the supplied NT_PRFPREG buffer.

 * Choose the appropriate helper for general registers, and then copy

 * the FCSR register separately.

 */

static int fpr_get(struct task_struct *target,

		   const struct user_regset *regset,

		   unsigned int pos, unsigned int count,

		   void *kbuf, void __user *ubuf)

{

	unsigned i;

	const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);

	int err;

	u64 fpr_val;



	/* XXX fcr31  */

	if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))

		err = fpr_get_fpa(target, &pos, &count, &kbuf, &ubuf);

	else

		err = fpr_get_msa(target, &pos, &count, &kbuf, &ubuf);

	if (err)

		return err;



	err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,

				  &target->thread.fpu.fcr31,

				  fcr31_pos, fcr31_pos + sizeof(u32));



	return err;

}



	if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))

		return user_regset_copyout(&pos, &count, &kbuf, &ubuf,

/*

 * Copy the supplied NT_PRFPREG buffer to the floating-point context,

 * !CONFIG_CPU_HAS_MSA variant.   Buffer slots correspond 1:1 to FP

 * context's general register slots.  Only general registers are copied.

 */

static int fpr_set_fpa(struct task_struct *target,

		       unsigned int *pos, unsigned int *count,

		       const void **kbuf, const void __user **ubuf)

{

	return user_regset_copyin(pos, count, kbuf, ubuf,

				  &target->thread.fpu,

					   0, sizeof(elf_fpregset_t));

				  0, NUM_FPU_REGS * sizeof(elf_fpreg_t));

}



	for (i = 0; i < NUM_FPU_REGS; i++) {

		fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0);

		err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,

/*

 * Copy the supplied NT_PRFPREG buffer to the floating-point context,

 * CONFIG_CPU_HAS_MSA variant.  Buffer slots are copied to lower 64

 * bits only of FP context's general register slots.  Only general

 * registers are copied.

 */

static int fpr_set_msa(struct task_struct *target,

		       unsigned int *pos, unsigned int *count,

		       const void **kbuf, const void __user **ubuf)

{

	unsigned int i;

	u64 fpr_val;

	int err;



	BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t));

	for (i = 0; i < NUM_FPU_REGS && *count > 0; i++) {

		err = user_regset_copyin(pos, count, kbuf, ubuf,

					 &fpr_val, i * sizeof(elf_fpreg_t),

					 (i + 1) * sizeof(elf_fpreg_t));

		if (err)

			return err;

		set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);

	}



	return 0;

}



/*

 * Copy the supplied NT_PRFPREG buffer to the floating-point context.

 * Choose the appropriate helper for general registers, and then copy

 * the FCSR register separately.

 *

 * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0',

 * which is supposed to have been guaranteed by the kernel before

 * calling us, e.g. in `ptrace_regset'.  We enforce that requirement,

 * so that we can safely avoid preinitializing temporaries for

 * partial register writes.

 */

static int fpr_set(struct task_struct *target,

		   const struct user_regset *regset,

		   unsigned int pos, unsigned int count,

		   const void *kbuf, const void __user *ubuf)

{

	unsigned i;

	const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);

	u32 fcr31;

	int err;

	u64 fpr_val;



	/* XXX fcr31  */

	BUG_ON(count % sizeof(elf_fpreg_t));



	if (pos + count > sizeof(elf_fpregset_t))

		return -EIO;



	init_fp_ctx(target);



	if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))

		return user_regset_copyin(&pos, &count, &kbuf, &ubuf,

					  &target->thread.fpu,

					  0, sizeof(elf_fpregset_t));

	if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))

		err = fpr_set_fpa(target, &pos, &count, &kbuf, &ubuf);

	else

		err = fpr_set_msa(target, &pos, &count, &kbuf, &ubuf);

	if (err)

		return err;



	BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t));

	for (i = 0; i < NUM_FPU_REGS && count >= sizeof(elf_fpreg_t); i++) {

	if (count > 0) {

		err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,

					 &fpr_val, i * sizeof(elf_fpreg_t),

					 (i + 1) * sizeof(elf_fpreg_t));

					 &fcr31,

					 fcr31_pos, fcr31_pos + sizeof(u32));

		if (err)

			return err;

		set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);



		ptrace_setfcr31(target, fcr31);

	}



	return 0;

	return err;

}



enum mips_regset {

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