clk: meson: eeclk: add init regs (19a18d42) · Commits · 戴 / test

Like the PLL and MPLL, the controller may require some magic setting to be applied on startup. This is needed when the initial setting is not applied by the boot ROM. The controller need to do it when the setting applies to several clock, like all the MPLLs in the case of g12a. Signed-off-by:

Jerome Brunet <jbrunet@baylibre.com>

drivers/clk/meson/meson-eeclk.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -34,6 +34,9 @@ int meson_eeclkc_probe(struct platform_device *pdev)
		return PTR_ERR(map);
		}

		if (data->init_count)
		regmap_multi_reg_write(map, data->init_regs, data->init_count);

		input = meson_clk_hw_register_input(dev, "xtal", IN_PREFIX "xtal", 0);
		if (IS_ERR(input)) {
		ret = PTR_ERR(input);

drivers/clk/meson/meson-eeclk.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -17,6 +17,8 @@ struct platform_device;
		struct meson_eeclkc_data {
		struct clk_regmap const regmap_clks;
		unsigned int regmap_clk_num;
		const struct reg_sequence *init_regs;
		unsigned int init_count;
		struct clk_hw_onecell_data *hw_onecell_data;
		};

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