Merge branch 'ENA-features-and-cosmetic-changes'

	u16 reserved;

	/* 1 :0 : reserved

	/* 0 : reserved

	 * 1 : rx_offset

	 * 2 : interrupt_moderation

	 * 31:3 : reserved

	 */

#define ENA_ADMIN_HOST_INFO_DEVICE_MASK                     GENMASK(7, 3)

#define ENA_ADMIN_HOST_INFO_BUS_SHIFT                       8

#define ENA_ADMIN_HOST_INFO_BUS_MASK                        GENMASK(15, 8)

#define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT                 1

#define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK                  BIT(1)

#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT      2

#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK       BIT(2)

#define ENA_REGS_ADMIN_INTR_MASK 1

#define ENA_POLL_MS	5

#define ENA_MIN_ADMIN_POLL_US 100

#define ENA_MAX_ADMIN_POLL_US 5000

/*****************************************************************************/

/*****************************************************************************/

static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,

					  u16 command_id, bool capture)

{

	if (unlikely(!queue->comp_ctx)) {

		pr_err("Completion context is NULL\n");

		return NULL;

	}

	if (unlikely(command_id >= queue->q_depth)) {

		pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",

		       command_id, queue->q_depth);

		return NULL;

	}

	if (unlikely(!queue->comp_ctx)) {

		pr_err("Completion context is NULL\n");

		return NULL;

	}

	if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {

		pr_err("Completion context is occupied\n");

		return NULL;

	if (unlikely(comp_status != 0))

		pr_err("admin command failed[%u]\n", comp_status);

	if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR))

		return -EINVAL;

	switch (comp_status) {

	case ENA_ADMIN_SUCCESS:

		return 0;

		return -EINVAL;

	}

	return 0;

	return -EINVAL;

}

static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)

{

	delay_us = max_t(u32, ENA_MIN_ADMIN_POLL_US, delay_us);

	delay_us = min_t(u32, delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);

	usleep_range(delay_us, 2 * delay_us);

}

static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,

	unsigned long flags = 0;

	unsigned long timeout;

	int ret;

	u32 exp = 0;

	timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout);

			goto err;

		}

		msleep(ENA_POLL_MS);

		ena_delay_exponential_backoff_us(exp++,

						 admin_queue->ena_dev->ena_min_poll_delay_us);

	}

	if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {

		/* The desc list entry size should be whole multiply of 8

		 * This requirement comes from __iowrite64_copy()

		 */

		pr_err("illegal entry size %d\n",

		       llq_info->desc_list_entry_size);

		pr_err("illegal entry size %d\n", llq_info->desc_list_entry_size);

		return -EINVAL;

	}

			if (admin_queue->auto_polling)

				admin_queue->polling = true;

		} else {

			pr_err("The ena device doesn't send a completion for the admin cmd %d status %d\n",

			pr_err("The ena device didn't send a completion for the admin cmd %d status %d\n",

			       comp_ctx->cmd_opcode, comp_ctx->status);

		}

		/* Check if shifted to polling mode.

static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,

				u16 exp_state)

{

	u32 val, i;

	u32 val, exp = 0;

	unsigned long timeout_stamp;

	/* Convert timeout from resolution of 100ms to ENA_POLL_MS */

	timeout = (timeout * 100) / ENA_POLL_MS;

	/* Convert timeout from resolution of 100ms to us resolution. */

	timeout_stamp = jiffies + usecs_to_jiffies(100 * 1000 * timeout);

	for (i = 0; i < timeout; i++) {

	while (1) {

		val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);

		if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {

			exp_state)

			return 0;

		msleep(ENA_POLL_MS);

	}

		if (time_is_before_jiffies(timeout_stamp))

			return -ETIME;

		ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);

	}

}

static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,

static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,

						 u16 intr_delay_resolution)

{

	/* Initial value of intr_delay_resolution might be 0 */

	u16 prev_intr_delay_resolution =

		ena_dev->intr_delay_resolution ?

		ena_dev->intr_delay_resolution :

		ENA_DEFAULT_INTR_DELAY_RESOLUTION;

	u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;

	if (!intr_delay_resolution) {

	if (unlikely(!intr_delay_resolution)) {

		pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");

		intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;

	}

{

	struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;

	unsigned long flags = 0;

	u32 exp = 0;

	spin_lock_irqsave(&admin_queue->q_lock, flags);

	while (atomic_read(&admin_queue->outstanding_cmds) != 0) {

		spin_unlock_irqrestore(&admin_queue->q_lock, flags);

		msleep(ENA_POLL_MS);

		ena_delay_exponential_backoff_us(exp++,

						 ena_dev->ena_min_poll_delay_us);

		spin_lock_irqsave(&admin_queue->q_lock, flags);

	}

	spin_unlock_irqrestore(&admin_queue->q_lock, flags);

	if (ret)

		goto error;

	admin_queue->ena_dev = ena_dev;

	admin_queue->running_state = true;

	return 0;

	struct ena_admin_aenq_entry *aenq_e;

	struct ena_admin_aenq_common_desc *aenq_common;

	struct ena_com_aenq *aenq  = &dev->aenq;

	unsigned long long timestamp;

	u64 timestamp;

	ena_aenq_handler handler_cb;

	u16 masked_head, processed = 0;

	u8 phase;

		 */

		dma_rmb();

		timestamp =

			(unsigned long long)aenq_common->timestamp_low |

			((unsigned long long)aenq_common->timestamp_high << 32);

		timestamp = (u64)aenq_common->timestamp_low |

			    ((u64)aenq_common->timestamp_high << 32);

		pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",

			 aenq_common->group, aenq_common->syndrom, timestamp);

	/* write the aenq doorbell after all AENQ descriptors were read */

	mb();

	writel_relaxed((u32)aenq->head,

		       dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);

	writel_relaxed((u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);

}

int ena_com_dev_reset(struct ena_com_dev *ena_dev,

			       enum ena_admin_hash_functions func,

			       const u8 *key, u16 key_len, u32 init_val)

{

	struct ena_rss *rss = &ena_dev->rss;

	struct ena_admin_feature_rss_flow_hash_control *hash_key;

	struct ena_admin_get_feat_resp get_resp;

	struct ena_admin_feature_rss_flow_hash_control *hash_key =

		rss->hash_key;

	enum ena_admin_hash_functions old_func;

	struct ena_rss *rss = &ena_dev->rss;

	int rc;

	hash_key = rss->hash_key;

	/* Make sure size is a mult of DWs */

	if (unlikely(key_len & 0x3))

		return -EINVAL;

	if (unlikely(rc))

		return rc;

	if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {

	if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {

		pr_err("Flow hash function %d isn't supported\n", func);

		return -EOPNOTSUPP;

	}

#define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0

#define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1

#define ENA_HASH_KEY_SIZE 40

#define ENA_HW_HINTS_NO_TIMEOUT	0xFFFF

#define ENA_FEATURE_MAX_QUEUE_EXT_VER 1

struct ena_com_admin_queue {

	void *q_dmadev;

	struct ena_com_dev *ena_dev;

	spinlock_t q_lock; /* spinlock for the admin queue */

	struct ena_comp_ctx *comp_ctx;

	struct ena_intr_moder_entry *intr_moder_tbl;

	struct ena_com_llq_info llq_info;

	u32 ena_min_poll_delay_us;

};

struct ena_com_dev_get_features_ctx {

 */

int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);

/* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism

/* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism

 * @ena_dev: ENA communication layer struct

 * @readless_supported: readless mode (enable/disable)

 */

/* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler

 * @ena_dev: ENA communication layer struct

 *

 * This method go over the admin completion queue and wake up all the pending

 * This method goes over the admin completion queue and wakes up all the pending

 * threads that wait on the commands wait event.

 *

 * @note: Should be called after MSI-X interrupt.

/* ena_com_aenq_intr_handler - AENQ interrupt handler

 * @ena_dev: ENA communication layer struct

 *

 * This method go over the async event notification queue and call the proper

 * This method goes over the async event notification queue and calls the proper

 * aenq handler.

 */

void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);

/* ena_com_wait_for_abort_completion - Wait for admin commands abort.

 * @ena_dev: ENA communication layer struct

 *

 * This method wait until all the outstanding admin commands will be completed.

 * This method waits until all the outstanding admin commands are completed.

 */

void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev);

/* ena_com_validate_version - Validate the device parameters

 * @ena_dev: ENA communication layer struct

 *

 * This method validate the device parameters are the same as the saved

 * This method verifies the device parameters are the same as the saved

 * parameters in ena_dev.

 * This method is useful after device reset, to validate the device mac address

 * and the device offloads are the same as before the reset.

 *

 * Retrieve the hash function from the device.

 *

 * @note: If the caller called ena_com_fill_hash_function but didn't flash

 * @note: If the caller called ena_com_fill_hash_function but didn't flush

 * it to the device, the new configuration will be lost.

 *

 * @return: 0 on Success and negative value otherwise.

 *

 * Retrieve the hash key.

 *

 * @note: If the caller called ena_com_fill_hash_key but didn't flash

 * @note: If the caller called ena_com_fill_hash_key but didn't flush

 * it to the device, the new configuration will be lost.

 *

 * @return: 0 on Success and negative value otherwise.

 *

 * Retrieve the hash control from the device.

 *

 * @note, If the caller called ena_com_fill_hash_ctrl but didn't flash

 * @note: If the caller called ena_com_fill_hash_ctrl but didn't flush

 * it to the device, the new configuration will be lost.

 *

 * @return: 0 on Success and negative value otherwise.

 *

 * Retrieve the RSS indirection table from the device.

 *

 * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash

 * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flush

 * it to the device, the new configuration will be lost.

 *

 * @return: 0 on Success and negative value otherwise.

/* ena_com_delete_debug_area - Free the debug area resources.

 * @ena_dev: ENA communication layer struct

 *

 * Free the allocate debug area.

 * Free the allocated debug area.

 */

void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);

/* ena_com_delete_host_info - Free the host info resources.

 * @ena_dev: ENA communication layer struct

 *

 * Free the allocate host info.

 * Free the allocated host info.

 */

void ena_com_delete_host_info(struct ena_com_dev *ena_dev);

 * @cmd_completion: command completion return value.

 * @cmd_comp_size: command completion size.

 * Submit an admin command and then wait until the device will return a

 * Submit an admin command and then wait until the device returns a

 * completion.

 * The completion will be copyed into cmd_comp.

 * The completion will be copied into cmd_comp.

 *

 * @return - 0 on success, negative value on failure.

 */

 * @intr_reg: interrupt register to update.

 * @rx_delay_interval: Rx interval in usecs

 * @tx_delay_interval: Tx interval in usecs

 * @unmask: unask enable/disable

 * @unmask: unmask enable/disable

 *

 * Prepare interrupt update register with the supplied parameters.

 */

	struct ena_eth_io_rx_cdesc_base *cdesc = NULL;

	u16 cdesc_idx = 0;

	u16 nb_hw_desc;

	u16 i;

	u16 i = 0;

	WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, "wrong Q type");

		return -ENOSPC;

	}

	for (i = 0; i < nb_hw_desc; i++) {

	cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx);

	ena_rx_ctx->pkt_offset = cdesc->offset;

	do {

		ena_buf[i].len = cdesc->length;

		ena_buf[i].req_id = cdesc->req_id;

		if (++i >= nb_hw_desc)

			break;

		cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx + i);

		ena_buf->len = cdesc->length;

		ena_buf->req_id = cdesc->req_id;

		ena_buf++;

	}

	} while (1);

	/* Update SQ head ptr */

	io_sq->next_to_comp += nb_hw_desc;

	desc->length = ena_buf->len;

	desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK;

	desc->ctrl |= ENA_ETH_IO_RX_DESC_LAST_MASK;

	desc->ctrl |= io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK;

	desc->ctrl |= ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;

	desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK |

		ENA_ETH_IO_RX_DESC_LAST_MASK |

		(io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK) |

		ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;

	desc->req_id = req_id;

	u32 hash;

	u16 descs;

	int max_bufs;

	u8 pkt_offset;

};

int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,

	writel(intr_reg->intr_control, io_cq->unmask_reg);

}

static inline int ena_com_free_desc(struct ena_com_io_sq *io_sq)

static inline int ena_com_free_q_entries(struct ena_com_io_sq *io_sq)

{

	u16 tail, next_to_comp, cnt;

	int temp;

	if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)

		return ena_com_free_desc(io_sq) >= required_buffers;

		return ena_com_free_q_entries(io_sq) >= required_buffers;

	/* This calculation doesn't need to be 100% accurate. So to reduce

	 * the calculation overhead just Subtract 2 lines from the free descs

	 */

	temp = required_buffers / io_sq->llq_info.descs_per_entry + 2;

	return ena_com_free_desc(io_sq) > temp;

	return ena_com_free_q_entries(io_sq) > temp;

}

static inline bool ena_com_meta_desc_changed(struct ena_com_io_sq *io_sq,