Commit 19828bd3 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'ioc3-eth-improvements' 



Thomas Bogendoerfer says:

====================
ioc3-eth improvements

In my patch series for splitting out the serial code from ioc3-eth
by using a MFD device there was one big patch for ioc3-eth.c,
which wasn't really usefull for reviews. This series contains the
ioc3-eth changes splitted in smaller steps and few more cleanups.
Only the conversion to MFD will be done later in a different series.

Changes in v3:
- no need to check skb == NULL before passing it to dev_kfree_skb_any
- free memory allocated with get_page(s) with free_page(s)
- allocate rx ring with just GFP_KERNEL
- add required alignment for rings in comments

Changes in v2:
- use net_err_ratelimited for printing various ioc3 errors
- added missing clearing of rx buf valid flags into ioc3_alloc_rings
- use __func__ for printing out of memory messages
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 1a914990 70359dbe

arch/mips/include/asm/sn/ioc3.h

+143 −214
Original line number Diff line number Diff line
@@ -3,169 +3,161 @@ 
 * Copyright (C) 1999, 2000 Ralf Baechle

 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.

 */

#ifndef _IOC3_H

#define _IOC3_H

#ifndef MIPS_SN_IOC3_H

#define MIPS_SN_IOC3_H



#include <linux/types.h>



/* serial port register map */

struct ioc3_serialregs {

	u32	sscr;

	u32	stpir;

	u32	stcir;

	u32	srpir;

	u32	srcir;

	u32	srtr;

	u32	shadow;

};



/* SUPERIO uart register map */

typedef volatile struct ioc3_uartregs {

struct ioc3_uartregs {

	union {

		volatile u8	rbr;	/* read only, DLAB == 0 */

		volatile u8	thr;	/* write only, DLAB == 0 */

		volatile u8	dll;	/* DLAB == 1 */

	} u1;

		u8	iu_rbr;	/* read only, DLAB == 0 */

		u8	iu_thr;	/* write only, DLAB == 0 */

		u8	iu_dll;	/* DLAB == 1 */

	};

	union {

		volatile u8	ier;	/* DLAB == 0 */

		volatile u8	dlm;	/* DLAB == 1 */

	} u2;

		u8	iu_ier;	/* DLAB == 0 */

		u8	iu_dlm;	/* DLAB == 1 */

	};

	union {

		volatile u8	iir;	/* read only */

		volatile u8	fcr;	/* write only */

	} u3;

	volatile u8	    iu_lcr;

	volatile u8	    iu_mcr;

	volatile u8	    iu_lsr;

	volatile u8	    iu_msr;

	volatile u8	    iu_scr;

} ioc3_uregs_t;



#define iu_rbr u1.rbr

#define iu_thr u1.thr

#define iu_dll u1.dll

#define iu_ier u2.ier

#define iu_dlm u2.dlm

#define iu_iir u3.iir

#define iu_fcr u3.fcr

		u8	iu_iir;	/* read only */

		u8	iu_fcr;	/* write only */

	};

	u8	iu_lcr;

	u8	iu_mcr;

	u8	iu_lsr;

	u8	iu_msr;

	u8	iu_scr;

};



struct ioc3_sioregs {

	volatile u8		fill[0x141];	/* starts at 0x141 */

	u8	fill[0x141];	/* starts at 0x141 */



	volatile u8		uartc;

	volatile u8		kbdcg;

	u8	uartc;

	u8	kbdcg;



	volatile u8		fill0[0x150 - 0x142 - 1];

	u8	fill0[0x150 - 0x142 - 1];



	volatile u8		pp_data;

	volatile u8		pp_dsr;

	volatile u8		pp_dcr;

	u8	pp_data;

	u8	pp_dsr;

	u8	pp_dcr;



	volatile u8		fill1[0x158 - 0x152 - 1];

	u8	fill1[0x158 - 0x152 - 1];



	volatile u8		pp_fifa;

	volatile u8		pp_cfgb;

	volatile u8		pp_ecr;

	u8	pp_fifa;

	u8	pp_cfgb;

	u8	pp_ecr;



	volatile u8		fill2[0x168 - 0x15a - 1];

	u8	fill2[0x168 - 0x15a - 1];



	volatile u8		rtcad;

	volatile u8		rtcdat;

	u8	rtcad;

	u8	rtcdat;



	volatile u8		fill3[0x170 - 0x169 - 1];

	u8	fill3[0x170 - 0x169 - 1];



	struct ioc3_uartregs	uartb;	/* 0x20170  */

	struct ioc3_uartregs	uarta;	/* 0x20178  */

};



struct ioc3_ethregs {

	u32	emcr;		/* 0x000f0  */

	u32	eisr;		/* 0x000f4  */

	u32	eier;		/* 0x000f8  */

	u32	ercsr;		/* 0x000fc  */

	u32	erbr_h;		/* 0x00100  */

	u32	erbr_l;		/* 0x00104  */

	u32	erbar;		/* 0x00108  */

	u32	ercir;		/* 0x0010c  */

	u32	erpir;		/* 0x00110  */

	u32	ertr;		/* 0x00114  */

	u32	etcsr;		/* 0x00118  */

	u32	ersr;		/* 0x0011c  */

	u32	etcdc;		/* 0x00120  */

	u32	ebir;		/* 0x00124  */

	u32	etbr_h;		/* 0x00128  */

	u32	etbr_l;		/* 0x0012c  */

	u32	etcir;		/* 0x00130  */

	u32	etpir;		/* 0x00134  */

	u32	emar_h;		/* 0x00138  */

	u32	emar_l;		/* 0x0013c  */

	u32	ehar_h;		/* 0x00140  */

	u32	ehar_l;		/* 0x00144  */

	u32	micr;		/* 0x00148  */

	u32	midr_r;		/* 0x0014c  */

	u32	midr_w;		/* 0x00150  */

};



struct ioc3_serioregs {

	u32	km_csr;		/* 0x0009c  */

	u32	k_rd;		/* 0x000a0  */

	u32	m_rd;		/* 0x000a4  */

	u32	k_wd;		/* 0x000a8  */

	u32	m_wd;		/* 0x000ac  */

};



/* Register layout of IOC3 in configuration space.  */

struct ioc3 {

	volatile u32	pad0[7];	/* 0x00000  */

	volatile u32	sio_ir;		/* 0x0001c  */

	volatile u32	sio_ies;	/* 0x00020  */

	volatile u32	sio_iec;	/* 0x00024  */

	volatile u32	sio_cr;		/* 0x00028  */

	volatile u32	int_out;	/* 0x0002c  */

	volatile u32	mcr;		/* 0x00030  */

	/* PCI Config Space registers  */

	u32	pci_id;		/* 0x00000  */

	u32	pci_scr;	/* 0x00004  */

	u32	pci_rev;	/* 0x00008  */

	u32	pci_lat;	/* 0x0000c  */

	u32	pci_addr;	/* 0x00010  */

	u32	pci_err_addr_l;	/* 0x00014  */

	u32	pci_err_addr_h;	/* 0x00018  */



	u32	sio_ir;		/* 0x0001c  */

	u32	sio_ies;	/* 0x00020  */

	u32	sio_iec;	/* 0x00024  */

	u32	sio_cr;		/* 0x00028  */

	u32	int_out;	/* 0x0002c  */

	u32	mcr;		/* 0x00030  */



	/* General Purpose I/O registers  */

	volatile u32	gpcr_s;		/* 0x00034  */

	volatile u32	gpcr_c;		/* 0x00038  */

	volatile u32	gpdr;		/* 0x0003c  */

	volatile u32	gppr_0;		/* 0x00040  */

	volatile u32	gppr_1;		/* 0x00044  */

	volatile u32	gppr_2;		/* 0x00048  */

	volatile u32	gppr_3;		/* 0x0004c  */

	volatile u32	gppr_4;		/* 0x00050  */

	volatile u32	gppr_5;		/* 0x00054  */

	volatile u32	gppr_6;		/* 0x00058  */

	volatile u32	gppr_7;		/* 0x0005c  */

	volatile u32	gppr_8;		/* 0x00060  */

	volatile u32	gppr_9;		/* 0x00064  */

	volatile u32	gppr_10;	/* 0x00068  */

	volatile u32	gppr_11;	/* 0x0006c  */

	volatile u32	gppr_12;	/* 0x00070  */

	volatile u32	gppr_13;	/* 0x00074  */

	volatile u32	gppr_14;	/* 0x00078  */

	volatile u32	gppr_15;	/* 0x0007c  */

	u32	gpcr_s;		/* 0x00034  */

	u32	gpcr_c;		/* 0x00038  */

	u32	gpdr;		/* 0x0003c  */

	u32	gppr[16];	/* 0x00040  */



	/* Parallel Port Registers  */

	volatile u32	ppbr_h_a;	/* 0x00080  */

	volatile u32	ppbr_l_a;	/* 0x00084  */

	volatile u32	ppcr_a;		/* 0x00088  */

	volatile u32	ppcr;		/* 0x0008c  */

	volatile u32	ppbr_h_b;	/* 0x00090  */

	volatile u32	ppbr_l_b;	/* 0x00094  */

	volatile u32	ppcr_b;		/* 0x00098  */

	u32	ppbr_h_a;	/* 0x00080  */

	u32	ppbr_l_a;	/* 0x00084  */

	u32	ppcr_a;		/* 0x00088  */

	u32	ppcr;		/* 0x0008c  */

	u32	ppbr_h_b;	/* 0x00090  */

	u32	ppbr_l_b;	/* 0x00094  */

	u32	ppcr_b;		/* 0x00098  */



	/* Keyboard and Mouse Registers	 */

	volatile u32	km_csr;		/* 0x0009c  */

	volatile u32	k_rd;		/* 0x000a0  */

	volatile u32	m_rd;		/* 0x000a4  */

	volatile u32	k_wd;		/* 0x000a8  */

	volatile u32	m_wd;		/* 0x000ac  */

	struct ioc3_serioregs	serio;



	/* Serial Port Registers  */

	volatile u32	sbbr_h;		/* 0x000b0  */

	volatile u32	sbbr_l;		/* 0x000b4  */

	volatile u32	sscr_a;		/* 0x000b8  */

	volatile u32	stpir_a;	/* 0x000bc  */

	volatile u32	stcir_a;	/* 0x000c0  */

	volatile u32	srpir_a;	/* 0x000c4  */

	volatile u32	srcir_a;	/* 0x000c8  */

	volatile u32	srtr_a;		/* 0x000cc  */

	volatile u32	shadow_a;	/* 0x000d0  */

	volatile u32	sscr_b;		/* 0x000d4  */

	volatile u32	stpir_b;	/* 0x000d8  */

	volatile u32	stcir_b;	/* 0x000dc  */

	volatile u32	srpir_b;	/* 0x000e0  */

	volatile u32	srcir_b;	/* 0x000e4  */

	volatile u32	srtr_b;		/* 0x000e8  */

	volatile u32	shadow_b;	/* 0x000ec  */

	u32	sbbr_h;		/* 0x000b0  */

	u32	sbbr_l;		/* 0x000b4  */

	struct ioc3_serialregs	port_a;

	struct ioc3_serialregs	port_b;



	/* Ethernet Registers */

	volatile u32	emcr;		/* 0x000f0  */

	volatile u32	eisr;		/* 0x000f4  */

	volatile u32	eier;		/* 0x000f8  */

	volatile u32	ercsr;		/* 0x000fc  */

	volatile u32	erbr_h;		/* 0x00100  */

	volatile u32	erbr_l;		/* 0x00104  */

	volatile u32	erbar;		/* 0x00108  */

	volatile u32	ercir;		/* 0x0010c  */

	volatile u32	erpir;		/* 0x00110  */

	volatile u32	ertr;		/* 0x00114  */

	volatile u32	etcsr;		/* 0x00118  */

	volatile u32	ersr;		/* 0x0011c  */

	volatile u32	etcdc;		/* 0x00120  */

	volatile u32	ebir;		/* 0x00124  */

	volatile u32	etbr_h;		/* 0x00128  */

	volatile u32	etbr_l;		/* 0x0012c  */

	volatile u32	etcir;		/* 0x00130  */

	volatile u32	etpir;		/* 0x00134  */

	volatile u32	emar_h;		/* 0x00138  */

	volatile u32	emar_l;		/* 0x0013c  */

	volatile u32	ehar_h;		/* 0x00140  */

	volatile u32	ehar_l;		/* 0x00144  */

	volatile u32	micr;		/* 0x00148  */

	volatile u32	midr_r;		/* 0x0014c  */

	volatile u32	midr_w;		/* 0x00150  */

	volatile u32	pad1[(0x20000 - 0x00154) / 4];

	struct ioc3_ethregs	eth;

	u32	pad1[(0x20000 - 0x00154) / 4];



	/* SuperIO Registers  XXX */

	struct ioc3_sioregs	sregs;	/* 0x20000 */

	volatile u32	pad2[(0x40000 - 0x20180) / 4];

	u32	pad2[(0x40000 - 0x20180) / 4];



	/* SSRAM Diagnostic Access */

	volatile u32	ssram[(0x80000 - 0x40000) / 4];

	u32	ssram[(0x80000 - 0x40000) / 4];



	/* Bytebus device offsets

	   0x80000 -   Access to the generic devices selected with   DEV0
@@ -178,6 +170,20 @@ struct ioc3 { 
	   0xFFFFF     bytebus DEV_SEL_3  */

};





#define PCI_LAT			0xc		/* Latency Timer */

#define PCI_SCR_DROP_MODE_EN	0x00008000	/* drop pios on parity err */

#define UARTA_BASE		0x178

#define UARTB_BASE		0x170



/*

 * Bytebus device space

 */

#define IOC3_BYTEBUS_DEV0	0x80000L

#define IOC3_BYTEBUS_DEV1	0xa0000L

#define IOC3_BYTEBUS_DEV2	0xc0000L

#define IOC3_BYTEBUS_DEV3	0xe0000L



/*

 * Ethernet RX Buffer

 */
@@ -233,14 +239,6 @@ struct ioc3_etxd { 
#define ETXD_B2CNT_MASK		0x7ff00000

#define ETXD_B2CNT_SHIFT	20



/*

 * Bytebus device space

 */

#define IOC3_BYTEBUS_DEV0	0x80000L

#define IOC3_BYTEBUS_DEV1	0xa0000L

#define IOC3_BYTEBUS_DEV2	0xc0000L

#define IOC3_BYTEBUS_DEV3	0xe0000L



/* ------------------------------------------------------------------------- */



/* Superio Registers (PIO Access) */
@@ -254,7 +252,7 @@ struct ioc3_etxd { 


/* SSRAM Diagnostic Access */

#define IOC3_SSRAM	IOC3_RAM_OFF	/* base of SSRAM diagnostic access */

#define IOC3_SSRAM_LEN	0x40000 /* 256kb (address space size, may not be fully populated) */

#define IOC3_SSRAM_LEN	0x40000	/* 256kb (addrspc sz, may not be populated) */

#define IOC3_SSRAM_DM	0x0000ffff	/* data mask */

#define IOC3_SSRAM_PM	0x00010000	/* parity mask */
@@ -294,10 +292,10 @@ struct ioc3_etxd { 
					   SIO_IR to assert */

#define KM_CSR_M_TO_EN	  0x00080000	/* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause

					   SIO_IR to assert */

#define KM_CSR_K_CLAMP_ONE	0x00100000	/* Pull K_CLK low after rec. one char */

#define KM_CSR_M_CLAMP_ONE	0x00200000	/* Pull M_CLK low after rec. one char */

#define KM_CSR_K_CLAMP_THREE	0x00400000	/* Pull K_CLK low after rec. three chars */

#define KM_CSR_M_CLAMP_THREE	0x00800000	/* Pull M_CLK low after rec. three char */

#define KM_CSR_K_CLAMP_1  0x00100000	/* Pull K_CLK low aft recv 1 char */

#define KM_CSR_M_CLAMP_1  0x00200000	/* Pull M_CLK low aft recv 1 char */

#define KM_CSR_K_CLAMP_3  0x00400000	/* Pull K_CLK low aft recv 3 chars */

#define KM_CSR_M_CLAMP_3  0x00800000	/* Pull M_CLK low aft recv 3 chars */



/* bitmasks for IOC3_K_RD and IOC3_M_RD */

#define KM_RD_DATA_2	0x000000ff	/* 3rd char recvd since last read */
@@ -440,10 +438,6 @@ struct ioc3_etxd { 
				 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)

#define SIO_IR_RT		(SIO_IR_RT_INT | SIO_IR_GEN_INT1)



/* macro to load pending interrupts */

#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \

				 PCI_INW(&((mem)->sio_ies_ro)))



/* bitmasks for SIO_CR */

#define SIO_CR_SIO_RESET	0x00000001	/* reset the SIO */

#define SIO_CR_SER_A_BASE	0x000000fe	/* DMA poll addr port A */
@@ -500,10 +494,11 @@ struct ioc3_etxd { 
#define GPCR_UARTB_MODESEL	0x40	/* pin is output to port B mode sel */

#define GPCR_UARTA_MODESEL	0x80	/* pin is output to port A mode sel */



#define GPPR_PHY_RESET_PIN	5	/* GIO pin controlling phy reset */

#define GPPR_UARTB_MODESEL_PIN	6	/* GIO pin controlling uart b mode select */

#define GPPR_UARTA_MODESEL_PIN	7	/* GIO pin controlling uart a mode select */

#define GPPR_PHY_RESET_PIN	5	/* GIO pin cntrlling phy reset */

#define GPPR_UARTB_MODESEL_PIN	6	/* GIO pin cntrlling uart b mode sel */

#define GPPR_UARTA_MODESEL_PIN	7	/* GIO pin cntrlling uart a mode sel */



/* ethernet */

#define EMCR_DUPLEX		0x00000001

#define EMCR_PROMISC		0x00000002

#define EMCR_PADEN		0x00000004
@@ -595,70 +590,4 @@ struct ioc3_etxd { 


#define MIDR_DATA_MASK		0x0000ffff



#define ERXBUF_IPCKSUM_MASK	0x0000ffff

#define ERXBUF_BYTECNT_MASK	0x07ff0000

#define ERXBUF_BYTECNT_SHIFT	16

#define ERXBUF_V		0x80000000



#define ERXBUF_CRCERR		0x00000001	/* aka RSV15 */

#define ERXBUF_FRAMERR		0x00000002	/* aka RSV14 */

#define ERXBUF_CODERR		0x00000004	/* aka RSV13 */

#define ERXBUF_INVPREAMB	0x00000008	/* aka RSV18 */

#define ERXBUF_LOLEN		0x00007000	/* aka RSV2_0 */

#define ERXBUF_HILEN		0x03ff0000	/* aka RSV12_3 */

#define ERXBUF_MULTICAST	0x04000000	/* aka RSV16 */

#define ERXBUF_BROADCAST	0x08000000	/* aka RSV17 */

#define ERXBUF_LONGEVENT	0x10000000	/* aka RSV19 */

#define ERXBUF_BADPKT		0x20000000	/* aka RSV20 */

#define ERXBUF_GOODPKT		0x40000000	/* aka RSV21 */

#define ERXBUF_CARRIER		0x80000000	/* aka RSV22 */



#define ETXD_BYTECNT_MASK	0x000007ff	/* total byte count */

#define ETXD_INTWHENDONE	0x00001000	/* intr when done */

#define ETXD_D0V		0x00010000	/* data 0 valid */

#define ETXD_B1V		0x00020000	/* buf 1 valid */

#define ETXD_B2V		0x00040000	/* buf 2 valid */

#define ETXD_DOCHECKSUM		0x00080000	/* insert ip cksum */

#define ETXD_CHKOFF_MASK	0x07f00000	/* cksum byte offset */

#define ETXD_CHKOFF_SHIFT	20



#define ETXD_D0CNT_MASK		0x0000007f

#define ETXD_B1CNT_MASK		0x0007ff00

#define ETXD_B1CNT_SHIFT	8

#define ETXD_B2CNT_MASK		0x7ff00000

#define ETXD_B2CNT_SHIFT	20



typedef enum ioc3_subdevs_e {

    ioc3_subdev_ether,

    ioc3_subdev_generic,

    ioc3_subdev_nic,

    ioc3_subdev_kbms,

    ioc3_subdev_ttya,

    ioc3_subdev_ttyb,

    ioc3_subdev_ecpp,

    ioc3_subdev_rt,

    ioc3_nsubdevs

} ioc3_subdev_t;



/* subdevice disable bits,

 * from the standard INFO_LBL_SUBDEVS

 */

#define IOC3_SDB_ETHER		(1<<ioc3_subdev_ether)

#define IOC3_SDB_GENERIC	(1<<ioc3_subdev_generic)

#define IOC3_SDB_NIC		(1<<ioc3_subdev_nic)

#define IOC3_SDB_KBMS		(1<<ioc3_subdev_kbms)

#define IOC3_SDB_TTYA		(1<<ioc3_subdev_ttya)

#define IOC3_SDB_TTYB		(1<<ioc3_subdev_ttyb)

#define IOC3_SDB_ECPP		(1<<ioc3_subdev_ecpp)

#define IOC3_SDB_RT		(1<<ioc3_subdev_rt)



#define IOC3_ALL_SUBDEVS	((1<<ioc3_nsubdevs)-1)



#define IOC3_SDB_SERIAL		(IOC3_SDB_TTYA|IOC3_SDB_TTYB)



#define IOC3_STD_SUBDEVS	IOC3_ALL_SUBDEVS



#define IOC3_INTA_SUBDEVS	IOC3_SDB_ETHER

#define IOC3_INTB_SUBDEVS	(IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)



#endif /* _IOC3_H */
 
#endif /* MIPS_SN_IOC3_H */

arch/mips/sgi-ip27/ip27-console.c

+3 −2
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ void prom_putchar(char c) 
{

	struct ioc3_uartregs *uart = console_uart();



	while ((uart->iu_lsr & 0x20) == 0);

	uart->iu_thr = c;

	while ((readb(&uart->iu_lsr) & 0x20) == 0)

		;

	writeb(c, &uart->iu_thr);

}

arch/mips/sgi-ip27/ip27-init.c

+0 −13
Original line number Diff line number Diff line
@@ -130,17 +130,6 @@ cnodeid_t get_compact_nodeid(void) 
	return NASID_TO_COMPACT_NODEID(get_nasid());

}



static inline void ioc3_eth_init(void)

{

	struct ioc3 *ioc3;

	nasid_t nid;



	nid = get_nasid();

	ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base;



	ioc3->eier = 0;

}



extern void ip27_reboot_setup(void);



void __init plat_mem_setup(void)
@@ -182,8 +171,6 @@ void __init plat_mem_setup(void) 
		panic("Kernel compiled for N mode.");

#endif



	ioc3_eth_init();



	ioport_resource.start = 0;

	ioport_resource.end = ~0UL;

	set_io_port_base(IO_BASE);

drivers/net/ethernet/sgi/ioc3-eth.c

+519 −519

File changed.

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