Commit 1950de14 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Add VECS semaphore bits 



Like the other rings, the VECS supports semaphores. The semaphore stuff
is a bit wonky so this patch on it's own should be nice for review.

This patch should have no functional impact.

v2: Fix the English parts of clarification (again, register names were
right, text was reversed) (Damien)
Restore the still valid invariant. (Damien)
The bsd semaphore register should be MI_SEMAPHORE_SYNC_VVE (Damien)

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4a3dd19d

drivers/gpu/drm/i915/i915_reg.h

+27 −13
Original line number Diff line number Diff line
@@ -265,13 +265,19 @@ 
#define  MI_SEMAPHORE_UPDATE	    (1<<21)

#define  MI_SEMAPHORE_COMPARE	    (1<<20)

#define  MI_SEMAPHORE_REGISTER	    (1<<18)

#define  MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS wait for RCS  (BRSYNC) */

#define  MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS wait for RCS  (VRSYNC) */

#define  MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */

#define  MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS wait for VCS  (BVSYNC) */

#define  MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS wait for BCS  (VBSYNC) */

#define  MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */

#define  MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */

#define  MI_SEMAPHORE_SYNC_INVALID  (1<<0)

#define  MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */

#define  MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */

#define  MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */

#define  MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */

#define  MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */

#define  MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */

#define  MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */

#define  MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */

#define  MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */

#define  MI_SEMAPHORE_SYNC_INVALID  (3<<16)

/*

 * 3D instructions used by the kernel

 */
@@ -581,6 +587,7 @@ 
#define RENDER_RING_BASE	0x02000

#define BSD_RING_BASE		0x04000

#define GEN6_BSD_RING_BASE	0x12000

#define VEBOX_RING_BASE		0x1a000

#define BLT_RING_BASE		0x22000

#define RING_TAIL(base)		((base)+0x30)

#define RING_HEAD(base)		((base)+0x34)
@@ -588,13 +595,20 @@ 
#define RING_CTL(base)		((base)+0x3c)

#define RING_SYNC_0(base)	((base)+0x40)

#define RING_SYNC_1(base)	((base)+0x44)

#define RING_SYNC_2(base)	((base)+0x48)

#define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))

#define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))

#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))

#define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))

#define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))

#define GEN6_VRSYNC	(RING_SYNC_1(GEN6_BSD_RING_BASE))

#define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))

#define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))

#define GEN6_NOSYNC 0

#define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))

#define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))

#define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))

#define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))

#define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))

#define GEN6_NOSYNC 0

#define RING_MAX_IDLE(base)	((base)+0x54)

#define RING_HWS_PGA(base)	((base)+0x80)

#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)

drivers/gpu/drm/i915/intel_ringbuffer.c

+6 −0
Original line number Diff line number Diff line
@@ -1688,9 +1688,11 @@ int intel_init_render_ring_buffer(struct drm_device *dev) 
		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;

		ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;

		ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;

		ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;

		ring->signal_mbox[RCS] = GEN6_NOSYNC;

		ring->signal_mbox[VCS] = GEN6_VRSYNC;

		ring->signal_mbox[BCS] = GEN6_BRSYNC;

		ring->signal_mbox[VECS] = GEN6_VERSYNC;

	} else if (IS_GEN5(dev)) {

		ring->add_request = pc_render_add_request;

		ring->flush = gen4_render_ring_flush;
@@ -1848,9 +1850,11 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) 
		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;

		ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;

		ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;

		ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;

		ring->signal_mbox[RCS] = GEN6_RVSYNC;

		ring->signal_mbox[VCS] = GEN6_NOSYNC;

		ring->signal_mbox[BCS] = GEN6_BVSYNC;

		ring->signal_mbox[VECS] = GEN6_VEVSYNC;

	} else {

		ring->mmio_base = BSD_RING_BASE;

		ring->flush = bsd_ring_flush;
@@ -1895,9 +1899,11 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) 
	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;

	ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;

	ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;

	ring->signal_mbox[RCS] = GEN6_RBSYNC;

	ring->signal_mbox[VCS] = GEN6_VBSYNC;

	ring->signal_mbox[BCS] = GEN6_NOSYNC;

	ring->signal_mbox[VECS] = GEN6_VEBSYNC;

	ring->init = init_ring_common;



	return intel_init_ring_buffer(dev, ring);

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