Merge tag 'davinci-for-v5.3/dt' of... (19339e6a) · Commits · 戴 / test

arch/arm/boot/dts/da850-evm.dts

+13 −0

Original line number	Diff line number	Diff line
		@@ -188,6 +188,19 @@
		};
		};

		&cpu {
		cpu-supply = <&vdcdc3_reg>;
		};

		/*
		* The standard da850-evm kits and SOM's are 375MHz so enable this operating
		* point by default. Higher frequencies must be enabled for custom boards with
		* other variants of the SoC.
		*/
		&opp_375 {
		status = "okay";
		};

		&sata {
		status = "okay";
		};

+36 −0

Original line number	Diff line number	Diff line
		@@ -154,12 +154,48 @@
		};
		};
		};

		cvdd: regulator0 {
		compatible = "regulator-fixed";
		regulator-name = "cvdd";
		regulator-min-microvolt = <1300000>;
		regulator-max-microvolt = <1300000>;
		regulator-always-on;
		regulator-boot-on;
		};
		};

		&ref_clk {
		clock-frequency = <24000000>;
		};

		&cpu {
		cpu-supply = <&cvdd>;
		};

		/*
		* LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are
		* valid. Unfortunately due to a problem with the DA8XX OHCI controller, we
		* can't enable more than one OPP by default, since the controller sometimes
		* becomes unresponsive after a transition. Fix the frequency at 456 MHz.
		*/

		&opp_100 {
		status = "disabled";
		};

		&opp_200 {
		status = "disabled";
		};

		&opp_300 {
		status = "disabled";
		};

		&opp_456 {
		status = "okay";
		};

		&pmx_core {
		status = "okay";

+30 −0

Original line number	Diff line number	Diff line
		@@ -122,6 +122,15 @@
		amp-supply = <&amp>;
		};

		cvdd: regulator0 {
		compatible = "regulator-fixed";
		regulator-name = "cvdd";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-always-on;
		regulator-boot-on;
		};

		/*
		* This is a 5V current limiting regulator that is shared by USB,
		* the sensor (input) ports, the motor (output) ports and the A/DC.
		@@ -201,6 +210,27 @@
		clock-frequency = <24000000>;
		};

		&cpu {
		cpu-supply = <&cvdd>;
		};

		/* since we have a fixed regulator, we can't run at these points */
		&opp_100 {
		status = "disabled";
		};

		&opp_200 {
		status = "disabled";
		};

		/*
		* The SoC is actually the 456MHz version, but because of the fixed regulator
		* This is the fastest we can go.
		*/
		&opp_375 {
		status = "okay";
		};

		&pmx_core {
		status = "okay";

+50 −0

Original line number	Diff line number	Diff line
		@@ -16,6 +16,56 @@
		reg = <0xc0000000 0x0>;
		};

		cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu: cpu@0 {
		compatible = "arm,arm926ej-s";
		device_type = "cpu";
		reg = <0>;
		clocks = <&psc0 14>;
		operating-points-v2 = <&opp_table>;
		};
		};

		opp_table: opp-table {
		compatible = "operating-points-v2";

		opp_100: opp100-100000000 {
		opp-hz = /bits/ 64 <100000000>;
		opp-microvolt = <1000000 950000 1050000>;
		};

		opp_200: opp110-200000000 {
		opp-hz = /bits/ 64 <200000000>;
		opp-microvolt = <1100000 1050000 1160000>;
		};

		opp_300: opp120-300000000 {
		opp-hz = /bits/ 64 <300000000>;
		opp-microvolt = <1200000 1140000 1320000>;
		};

		/*
		* Original silicon was 300MHz max, so higher frequencies
		* need to be enabled on a per-board basis if the chip is
		* capable.
		*/

		opp_375: opp120-375000000 {
		status = "disabled";
		opp-hz = /bits/ 64 <375000000>;
		opp-microvolt = <1200000 1140000 1320000>;
		};

		opp_456: opp130-456000000 {
		status = "disabled";
		opp-hz = /bits/ 64 <456000000>;
		opp-microvolt = <1300000 1250000 1350000>;
		};
		};

		arm {
		#address-cells = <1>;
		#size-cells = <1>;

+1 −0

Original line number	Diff line number	Diff line
		@@ -45,6 +45,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
		CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
		CONFIG_CPU_FREQ_GOV_POWERSAVE=m
		CONFIG_CPU_FREQ_GOV_ONDEMAND=m
		CONFIG_CPUFREQ_DT=m
		CONFIG_CPU_IDLE=y
		CONFIG_NET=y
		CONFIG_PACKET=y