Commit 192a5e8c authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'oxnas-arm-soc-for-4.10-v2' of https://github.com/OXNAS/linux into next/soc

Pull "ARM: OXNAS SoC updates for 4.10" from Neil Armstrong:

- Add SMP support for the Oxford Semiconductor OX820 SoC
from http://lkml.kernel.org/r/20161021085848.1754-1-narmstrong@baylibre.com

Changes since v1 Pull Request at : http://lkml.kernel.org/r/1305c61f-b1ef-7caf-7788-67e2b907e873@baylibre.com
 - Clarify copyright dates in commit message
 - Remove linux/arch/... lines from the top of the files

* tag 'oxnas-arm-soc-for-4.10-v2' of https://github.com/OXNAS/linux:
  ARM: oxnas: Add OX820 config and makefile entry
  ARM: oxnas: Add OX820 SMP support
parents 048f789b e330ea5e
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@@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_NETX)		+= netx
machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
machine-$(CONFIG_ARCH_NSPIRE)		+= nspire
machine-$(CONFIG_ARCH_OXNAS)		+= oxnas
machine-$(CONFIG_ARCH_OMAP1)		+= omap1
machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
+21 −9
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menuconfig ARCH_OXNAS
	bool "Oxford Semiconductor OXNAS Family SoCs"
	select ARCH_HAS_RESET_CONTROLLER
	select COMMON_CLK_OXNAS
	select GPIOLIB
	select MFD_SYSCON
	select OXNAS_RPS_TIMER
	select PINCTRL_OXNAS
	select RESET_CONTROLLER
	select RESET_OXNAS
	select VERSATILE_FPGA_IRQ
	select PINCTRL
	depends on ARCH_MULTI_V5
	depends on ARCH_MULTI_V5 || ARCH_MULTI_V6
	help
	  Support for OxNas SoC family developed by Oxford Semiconductor.

@@ -11,16 +18,21 @@ if ARCH_OXNAS

config MACH_OX810SE
	bool "Support OX810SE Based Products"
	select ARCH_HAS_RESET_CONTROLLER
	select COMMON_CLK_OXNAS
	depends on ARCH_MULTI_V5
	select CPU_ARM926T
	select MFD_SYSCON
	select OXNAS_RPS_TIMER
	select PINCTRL_OXNAS
	select RESET_CONTROLLER
	select RESET_OXNAS
	select VERSATILE_FPGA_IRQ
	help
	  Include Support for the Oxford Semiconductor OX810SE SoC Based Products.

config MACH_OX820
	bool "Support OX820 Based Products"
	depends on ARCH_MULTI_V6
	select ARM_GIC
	select DMA_CACHE_RWFO if SMP
	select CPU_V6K
	select HAVE_SMP
	select HAVE_ARM_SCU if SMP
	select HAVE_ARM_TWD if SMP
	help
	  Include Support for the Oxford Semiconductor OX820 SoC Based Products.

endif
+2 −0
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obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) 	+= hotplug.o
+26 −0
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/*
 * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
 * Copyright (c) 2003 ARM Limited
 * All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/linkage.h>
#include <linux/init.h>

	__INIT

/*
 * OX820 specific entry point for secondary CPUs.
 */
ENTRY(ox820_secondary_startup)
	mov r4, #0
	/* invalidate both caches and branch target cache */
	mcr p15, 0, r4, c7, c7, 0
	/*
	 * we've been released from the holding pen: secondary_stack
	 * should now contain the SVC stack for this core
	 */
	b	secondary_startup
+109 −0
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/*
 *  Copyright (C) 2002 ARM Ltd.
 *  All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>

#include <asm/cp15.h>
#include <asm/smp_plat.h>

static inline void cpu_enter_lowpower(void)
{
	unsigned int v;

	asm volatile(
	"	mcr	p15, 0, %1, c7, c5, 0\n"
	"	mcr	p15, 0, %1, c7, c10, 4\n"
	/*
	 * Turn off coherency
	 */
	"	mrc	p15, 0, %0, c1, c0, 1\n"
	"	bic	%0, %0, #0x20\n"
	"	mcr	p15, 0, %0, c1, c0, 1\n"
	"	mrc	p15, 0, %0, c1, c0, 0\n"
	"	bic	%0, %0, %2\n"
	"	mcr	p15, 0, %0, c1, c0, 0\n"
	  : "=&r" (v)
	  : "r" (0), "Ir" (CR_C)
	  : "cc");
}

static inline void cpu_leave_lowpower(void)
{
	unsigned int v;

	asm volatile(	"mrc	p15, 0, %0, c1, c0, 0\n"
	"	orr	%0, %0, %1\n"
	"	mcr	p15, 0, %0, c1, c0, 0\n"
	"	mrc	p15, 0, %0, c1, c0, 1\n"
	"	orr	%0, %0, #0x20\n"
	"	mcr	p15, 0, %0, c1, c0, 1\n"
	  : "=&r" (v)
	  : "Ir" (CR_C)
	  : "cc");
}

static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
	/*
	 * there is no power-control hardware on this platform, so all
	 * we can do is put the core into WFI; this is safe as the calling
	 * code will have already disabled interrupts
	 */
	for (;;) {
		/*
		 * here's the WFI
		 */
		asm(".word	0xe320f003\n"
		    :
		    :
		    : "memory", "cc");

		if (pen_release == cpu_logical_map(cpu)) {
			/*
			 * OK, proper wakeup, we're done
			 */
			break;
		}

		/*
		 * Getting here, means that we have come out of WFI without
		 * having been woken up - this shouldn't happen
		 *
		 * Just note it happening - when we're woken, we can report
		 * its occurrence.
		 */
		(*spurious)++;
	}
}

/*
 * platform-specific code to shutdown a CPU
 *
 * Called with IRQs disabled
 */
void ox820_cpu_die(unsigned int cpu)
{
	int spurious = 0;

	/*
	 * we're ready for shutdown now, so do it
	 */
	cpu_enter_lowpower();
	platform_do_lowpower(cpu, &spurious);

	/*
	 * bring this CPU back into the world of cache
	 * coherency, and then restore interrupts
	 */
	cpu_leave_lowpower();

	if (spurious)
		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
}
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