Commit 1929d0b5 authored by Vignesh R's avatar Vignesh R Committed by Tony Lindgren
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ARM: dts: DRA7: add entry for qspi mmap region 



Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
update the binding documents for the controller to document this change.

Signed-off-by: default avatarVignesh R <vigneshr@ti.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent d01d8799

Documentation/devicetree/bindings/spi/ti_qspi.txt

+17 −0
Original line number Diff line number Diff line
@@ -15,6 +15,10 @@ Recommended properties: 
- spi-max-frequency: Definition as per

                     Documentation/devicetree/bindings/spi/spi-bus.txt



Optional properties:

- syscon-chipselects: Handle to system control region contains QSPI

		      chipselect register and offset of that register.



Example:



qspi: qspi@4b300000 {
@@ -26,3 +30,16 @@ qspi: qspi@4b300000 { 
	spi-max-frequency = <25000000>;

	ti,hwmods = "qspi";

};



For dra7xx:

qspi: qspi@4b300000 {

	compatible = "ti,dra7xxx-qspi";

	reg = <0x4b300000 0x100>,

	      <0x5c000000 0x4000000>,

	reg-names = "qspi_base", "qspi_mmap";

	syscon-chipselects = <&scm_conf 0x558>;

	#address-cells = <1>;

	#size-cells = <0>;

	spi-max-frequency = <48000000>;

	ti,hwmods = "qspi";

};

arch/arm/boot/dts/dra7.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -1154,8 +1154,10 @@ 


		qspi: qspi@4b300000 {

			compatible = "ti,dra7xxx-qspi";

			reg = <0x4b300000 0x100>;

			reg-names = "qspi_base";

			reg = <0x4b300000 0x100>,

			      <0x5c000000 0x4000000>;

			reg-names = "qspi_base", "qspi_mmap";

			syscon-chipselects = <&scm_conf 0x558>;

			#address-cells = <1>;

			#size-cells = <0>;

			ti,hwmods = "qspi";

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