Commit 1925e7d3 authored Apr 11, 2019 by Alex Deucher

drm/amdgpu/gmc9: fix VM_L2_CNTL3 programming



Got accidently dropped when 2+1 level support was added.

Fixes: 6a42fd6f ("drm/amdgpu: implement 2+1 PD support for Raven v3")
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

parent b575f10d

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -182,6 +182,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
		L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
		}
		WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);

		tmp = mmVM_L2_CNTL4_DEFAULT;
		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

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