Commit 19167eb0 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915: Reorder intel_psr2_config_valid() 



Future patches will bring PSR2 selective fetch configuration
validation but most of the configuration checks will be used for HW
tracking and selective fetch so the reoder was necessary.

Reviewed-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200626010151.221388-2-jose.souza@intel.com
parent 093a3a30

drivers/gpu/drm/i915/display/intel_psr.c

+25 −25
Original line number Diff line number Diff line
@@ -681,21 +681,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
		return false;

	}



	/*

	 * Some platforms lack PSR2 HW tracking and instead require manual

	 * tracking by software.  In this case, the driver is required to track

	 * the areas that need updates and program hardware to send selective

	 * updates.

	 *

	 * So until the software tracking is implemented, PSR2 needs to be

	 * disabled for platforms without PSR2 HW tracking.

	 */

	if (!HAS_PSR_HW_TRACKING(dev_priv)) {

		drm_dbg_kms(&dev_priv->drm,

			    "No PSR2 HW tracking in the platform\n");

		return false;

	}



	/*

	 * DSC and PSR2 cannot be enabled simultaneously. If a requested

	 * resolution requires DSC to be enabled, priority is given to DSC
@@ -707,6 +692,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
		return false;

	}



	if (crtc_state->crc_enabled) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled because it would inhibit pipe CRC calculation\n");

		return false;

	}



	if (INTEL_GEN(dev_priv) >= 12) {

		psr_max_h = 5120;

		psr_max_v = 3200;
@@ -721,14 +712,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
		max_bpp = 24;

	}



	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",

			    crtc_hdisplay, crtc_vdisplay,

			    psr_max_h, psr_max_v);

		return false;

	}



	if (crtc_state->pipe_bpp > max_bpp) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, pipe bpp %d > max supported %d\n",
@@ -749,9 +732,26 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
		return false;

	}



	if (crtc_state->crc_enabled) {

	/*

	 * Some platforms lack PSR2 HW tracking and instead require manual

	 * tracking by software.  In this case, the driver is required to track

	 * the areas that need updates and program hardware to send selective

	 * updates.

	 *

	 * So until the software tracking is implemented, PSR2 needs to be

	 * disabled for platforms without PSR2 HW tracking.

	 */

	if (!HAS_PSR_HW_TRACKING(dev_priv)) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled because it would inhibit pipe CRC calculation\n");

			    "No PSR2 HW tracking in the platform\n");

		return false;

	}



	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",

			    crtc_hdisplay, crtc_vdisplay,

			    psr_max_h, psr_max_v);

		return false;

	}

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