Commit 18c79d76 authored by Abhijeet Dharmapurikar's avatar Abhijeet Dharmapurikar Committed by Greg Kroah-Hartman
Browse files

msm_serial: fix serial on trout 



Set the mnd counter based on uartclk. This fixes a problem
on 7x30 where the uartclk is 19.2Mhz rather than the usual
4.8Mhz.

Trout incorrectly reports uartclk to be running at 19.2Mhz
It is actually running at 4.8Mhz.  For trout force mnd
counter values as if uartclk was fed by tcxo/4.

Signed-off-by: default avatarAbhijeet Dharmapurikar <adharmap@codeaurora.org>
[dwalker@codeaurora.org: inlined, moved into header, added comments.]
Signed-off-by: default avatarDaniel Walker <dwalker@codeaurora.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent ad845636

drivers/serial/msm_serial.c

+3 −18
Original line number Diff line number Diff line
@@ -41,19 +41,6 @@ struct msm_port { 
	unsigned int		imr;

};



#define UART_TO_MSM(uart_port)	((struct msm_port *) uart_port)



static inline void msm_write(struct uart_port *port, unsigned int val,

			     unsigned int off)

{

	__raw_writel(val, port->membase + off);

}



static inline unsigned int msm_read(struct uart_port *port, unsigned int off)

{

	return __raw_readl(port->membase + off);

}



static void msm_stop_tx(struct uart_port *port)

{

	struct msm_port *msm_port = UART_TO_MSM(port);
@@ -320,11 +307,7 @@ static void msm_init_clock(struct uart_port *port) 
	struct msm_port *msm_port = UART_TO_MSM(port);



	clk_enable(msm_port->clk);



	msm_write(port, 0xC0, UART_MREG);

	msm_write(port, 0xB2, UART_NREG);

	msm_write(port, 0x7D, UART_DREG);

	msm_write(port, 0x1C, UART_MNDREG);

	msm_serial_set_mnd_regs(port);

}



static int msm_startup(struct uart_port *port)
@@ -706,6 +689,8 @@ static int __init msm_serial_probe(struct platform_device *pdev) 
	if (unlikely(IS_ERR(msm_port->clk)))

		return PTR_ERR(msm_port->clk);

	port->uartclk = clk_get_rate(msm_port->clk);

	printk(KERN_INFO "uartclk = %d\n", port->uartclk);





	resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (unlikely(!resource))

drivers/serial/msm_serial.h

+56 −0
Original line number Diff line number Diff line
@@ -114,4 +114,60 @@ 
#define UART_MISR	0x0010

#define UART_ISR	0x0014



#define UART_TO_MSM(uart_port)	((struct msm_port *) uart_port)



static inline

void msm_write(struct uart_port *port, unsigned int val, unsigned int off)

{

	__raw_writel(val, port->membase + off);

}



static inline

unsigned int msm_read(struct uart_port *port, unsigned int off)

{

	return __raw_readl(port->membase + off);

}



/*

 * Setup the MND registers to use the TCXO clock.

 */

static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)

{

	msm_write(port, 0x06, UART_MREG);

	msm_write(port, 0xF1, UART_NREG);

	msm_write(port, 0x0F, UART_DREG);

	msm_write(port, 0x1A, UART_MNDREG);

}



/*

 * Setup the MND registers to use the TCXO clock divided by 4.

 */

static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)

{

	msm_write(port, 0x18, UART_MREG);

	msm_write(port, 0xF6, UART_NREG);

	msm_write(port, 0x0F, UART_DREG);

	msm_write(port, 0x0A, UART_MNDREG);

}



static inline

void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)

{

	if (port->uartclk == 19200000)

		msm_serial_set_mnd_regs_tcxo(port);

	else

		msm_serial_set_mnd_regs_tcxoby4(port);

}



/*

 * TROUT has a specific defect that makes it report it's uartclk

 * as 19.2Mhz (TCXO) when it's actually 4.8Mhz (TCXO/4). This special

 * cases TROUT to use the right clock.

 */

#ifdef CONFIG_MACH_TROUT

#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_tcxoby4

#else

#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk

#endif



#endif	/* __DRIVERS_SERIAL_MSM_SERIAL_H */

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