Commit 18c71ce9 authored by Tom Lendacky's avatar Tom Lendacky Committed by Brijesh Singh
Browse files

x86/CPU/AMD: Add the Secure Encrypted Virtualization CPU feature 



Update the CPU features to include identifying and reporting on the
Secure Encrypted Virtualization (SEV) feature.  SEV is identified by
CPUID 0x8000001f, but requires BIOS support to enable it (set bit 23 of
MSR_K8_SYSCFG and set bit 0 of MSR_K7_HWCR).  Only show the SEV feature
as available if reported by CPUID and enabled by BIOS.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: kvm@vger.kernel.org
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarBrijesh Singh <brijesh.singh@amd.com>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
parent b38defdb

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -201,6 +201,7 @@ 
#define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */

#define X86_FEATURE_PROC_FEEDBACK	( 7*32+ 9) /* AMD ProcFeedbackInterface */

#define X86_FEATURE_SME			( 7*32+10) /* AMD Secure Memory Encryption */

#define X86_FEATURE_SEV			( 7*32+11) /* AMD Secure Encrypted Virtualization */



#define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory Number */

#define X86_FEATURE_INTEL_PT		( 7*32+15) /* Intel Processor Trace */

arch/x86/include/asm/msr-index.h

+2 −0
Original line number Diff line number Diff line
@@ -382,6 +382,8 @@ 
#define MSR_K7_PERFCTR3			0xc0010007

#define MSR_K7_CLK_CTL			0xc001001b

#define MSR_K7_HWCR			0xc0010015

#define MSR_K7_HWCR_SMMLOCK_BIT		0

#define MSR_K7_HWCR_SMMLOCK		BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)

#define MSR_K7_FID_VID_CTL		0xc0010041

#define MSR_K7_FID_VID_STATUS		0xc0010042

arch/x86/kernel/cpu/amd.c

+46 −20
Original line number Diff line number Diff line
@@ -556,6 +556,51 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 
	}

}



static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)

{

	u64 msr;



	/*

	 * BIOS support is required for SME and SEV.

	 *   For SME: If BIOS has enabled SME then adjust x86_phys_bits by

	 *	      the SME physical address space reduction value.

	 *	      If BIOS has not enabled SME then don't advertise the

	 *	      SME feature (set in scattered.c).

	 *   For SEV: If BIOS has not enabled SEV then don't advertise the

	 *            SEV feature (set in scattered.c).

	 *

	 *   In all cases, since support for SME and SEV requires long mode,

	 *   don't advertise the feature under CONFIG_X86_32.

	 */

	if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {

		/* Check if memory encryption is enabled */

		rdmsrl(MSR_K8_SYSCFG, msr);

		if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))

			goto clear_all;



		/*

		 * Always adjust physical address bits. Even though this

		 * will be a value above 32-bits this is still done for

		 * CONFIG_X86_32 so that accurate values are reported.

		 */

		c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;



		if (IS_ENABLED(CONFIG_X86_32))

			goto clear_all;



		rdmsrl(MSR_K7_HWCR, msr);

		if (!(msr & MSR_K7_HWCR_SMMLOCK))

			goto clear_sev;



		return;



clear_all:

		clear_cpu_cap(c, X86_FEATURE_SME);

clear_sev:

		clear_cpu_cap(c, X86_FEATURE_SEV);

	}

}



static void early_init_amd(struct cpuinfo_x86 *c)

{

	u32 dummy;
@@ -627,26 +672,7 @@ static void early_init_amd(struct cpuinfo_x86 *c) 
	if (cpu_has_amd_erratum(c, amd_erratum_400))

		set_cpu_bug(c, X86_BUG_AMD_E400);



	/*

	 * BIOS support is required for SME. If BIOS has enabled SME then

	 * adjust x86_phys_bits by the SME physical address space reduction

	 * value. If BIOS has not enabled SME then don't advertise the

	 * feature (set in scattered.c). Also, since the SME support requires

	 * long mode, don't advertise the feature under CONFIG_X86_32.

	 */

	if (cpu_has(c, X86_FEATURE_SME)) {

		u64 msr;



		/* Check if SME is enabled */

		rdmsrl(MSR_K8_SYSCFG, msr);

		if (msr & MSR_K8_SYSCFG_MEM_ENCRYPT) {

			c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;

			if (IS_ENABLED(CONFIG_X86_32))

				clear_cpu_cap(c, X86_FEATURE_SME);

		} else {

			clear_cpu_cap(c, X86_FEATURE_SME);

		}

	}

	early_detect_mem_encrypt(c);

}



static void init_amd_k8(struct cpuinfo_x86 *c)

arch/x86/kernel/cpu/scattered.c

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ static const struct cpuid_bit cpuid_bits[] = { 
	{ X86_FEATURE_CPB,		CPUID_EDX,  9, 0x80000007, 0 },

	{ X86_FEATURE_PROC_FEEDBACK,    CPUID_EDX, 11, 0x80000007, 0 },

	{ X86_FEATURE_SME,		CPUID_EAX,  0, 0x8000001f, 0 },

	{ X86_FEATURE_SEV,		CPUID_EAX,  1, 0x8000001f, 0 },

	{ 0, 0, 0, 0, 0 }

};

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