Merge tag 'ixp4xx-for-armsoc' of...

# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel IXP4xx Device Tree Bindings

maintainers:

  - Linus Walleij <linus.walleij@linaro.org>

properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - linksys,nslu2

          - const: intel,ixp42x

      - items:

          - enum:

              - gateworks,gw2358

          - const: intel,ixp43x

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2019 Linaro Ltd.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP4xx Network Processing Engine

maintainers:

  - Linus Walleij <linus.walleij@linaro.org>

description: |

  On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small

  processor that can load a firmware to perform offloading of networking

  and crypto tasks. It also manages the MDIO bus to the ethernet PHYs

  on the IXP4xx platform. All IXP4xx platforms have three NPEs at

  consecutive memory locations. They are all included in the same

  device node since they are not independent of each other.

properties:

  compatible:

    oneOf:

      - items:

          - const: intel,ixp4xx-network-processing-engine

  reg:

    minItems: 3

    maxItems: 3

    items:

      - description: NPE0 register range

      - description: NPE1 register range

      - description: NPE2 register range

required:

  - compatible

  - reg

examples:

  - |

    npe@c8006000 {

         compatible = "intel,ixp4xx-network-processing-engine";

         reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;

    };

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2018 Linaro Ltd.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/interrupt/intel-ixp4xx-interrupt.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP4xx XScale Networking Processors Interrupt Controller

maintainers:

  - Linus Walleij <linus.walleij@linaro.org>

description: |

  This interrupt controller is found in the Intel IXP4xx processors.

  Some processors have 32 interrupts, some have up to 64 interrupts.

  The exact number of interrupts is determined from the compatible

  string.

  The distinct IXP4xx families with different interrupt controller

  variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four

  families were the only ones to reach the developer and consumer

  market.

properties:

  compatible:

    items:

      - enum:

        - intel,ixp42x-interrupt

        - intel,ixp43x-interrupt

        - intel,ixp45x-interrupt

        - intel,ixp46x-interrupt

  reg:

    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':

    const: 2

required:

  - compatible

  - reg

  - interrupt-controller

  - '#interrupt-cells'

examples:

  - |

    intcon: interrupt-controller@c8003000 {

        compatible = "intel,ixp43x-interrupt";

        reg = <0xc8003000 0x100>;

        interrupt-controller;

        #interrupt-cells = <2>;

    };

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2019 Linaro Ltd.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/misc/intel-ixp4xx-ahb-queue-manager.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP4xx AHB Queue Manager

maintainers:

  - Linus Walleij <linus.walleij@linaro.org>

description: |

  The IXP4xx AHB Queue Manager maintains queues as circular buffers in

  an 8KB embedded SRAM along with hardware pointers. It is used by both

  the XScale processor and the NPEs (Network Processing Units) in the

  IXP4xx for accelerating queues, especially for networking. Clients pick

  queues from the queue manager with foo-queue = <&qmgr N> where the

  &qmgr is a phandle to the queue manager and N is the queue resource

  number. The queue resources available and their specific purpose

  on a certain IXP4xx system will vary.

properties:

  compatible:

    items:

      - const: intel,ixp4xx-ahb-queue-manager

  reg:

    maxItems: 1

  interrupts:

    items:

      - description: Interrupt for queues 0-31

      - description: Interrupt for queues 32-63

required:

  - compatible

  - reg

  - interrupts

examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    qmgr: queue-manager@60000000 {

         compatible = "intel,ixp4xx-ahb-queue-manager";

         reg = <0x60000000 0x4000>;

         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;

    };

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2018 Linaro Ltd.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/timer/intel-ixp4xx-timer.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP4xx XScale Networking Processors Timers

maintainers:

  - Linus Walleij <linus.walleij@linaro.org>

description: This timer is found in the Intel IXP4xx processors.

properties:

  compatible:

    items:

      - const: intel,ixp4xx-timer

  reg:

    description: Should contain registers location and length

  interrupts:

    minItems: 1

    maxItems: 2

    items:

      - description: Timer 1 interrupt

      - description: Timer 2 interrupt

required:

  - compatible

  - reg

  - interrupts

examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    timer@c8005000 {

        compatible = "intel,ixp4xx-timer";

        reg = <0xc8005000 0x100>;

        interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;

    };