Commit 183ad366 authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC 



Add a CPU clock to every CPU node and CPU OPP tables to use the
generic cpufreq driver.  All the CPUs in each cluster share the
same OPP table.

Note:
clock-latency-ns (300ns) was calculated based on the CPU-gear switch
sequencer spec; it takes 12 clock cycles on the sequencer running
at 50 MHz, plus a bit additional latency.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent bdb81836

arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

+84 −0
Original line number Diff line number Diff line
@@ -79,28 +79,112 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a72", "arm,armv8";

			reg = <0 0x000>;

			clocks = <&sys_clk 32>;

			enable-method = "psci";

			operating-points-v2 = <&cluster0_opp>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a72", "arm,armv8";

			reg = <0 0x001>;

			clocks = <&sys_clk 32>;

			enable-method = "psci";

			operating-points-v2 = <&cluster0_opp>;

		};



		cpu2: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0 0x100>;

			clocks = <&sys_clk 33>;

			enable-method = "psci";

			operating-points-v2 = <&cluster1_opp>;

		};



		cpu3: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0 0x101>;

			clocks = <&sys_clk 33>;

			enable-method = "psci";

			operating-points-v2 = <&cluster1_opp>;

		};

	};



	cluster0_opp: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@250000000 {

			opp-hz = /bits/ 64 <250000000>;

			clock-latency-ns = <300>;

		};

		opp@275000000 {

			opp-hz = /bits/ 64 <275000000>;

			clock-latency-ns = <300>;

		};

		opp@500000000 {

			opp-hz = /bits/ 64 <500000000>;

			clock-latency-ns = <300>;

		};

		opp@550000000 {

			opp-hz = /bits/ 64 <550000000>;

			clock-latency-ns = <300>;

		};

		opp@666667000 {

			opp-hz = /bits/ 64 <666667000>;

			clock-latency-ns = <300>;

		};

		opp@733334000 {

			opp-hz = /bits/ 64 <733334000>;

			clock-latency-ns = <300>;

		};

		opp@1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			clock-latency-ns = <300>;

		};

		opp@1100000000 {

			opp-hz = /bits/ 64 <1100000000>;

			clock-latency-ns = <300>;

		};

	};



	cluster1_opp: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@250000000 {

			opp-hz = /bits/ 64 <250000000>;

			clock-latency-ns = <300>;

		};

		opp@275000000 {

			opp-hz = /bits/ 64 <275000000>;

			clock-latency-ns = <300>;

		};

		opp@500000000 {

			opp-hz = /bits/ 64 <500000000>;

			clock-latency-ns = <300>;

		};

		opp@550000000 {

			opp-hz = /bits/ 64 <550000000>;

			clock-latency-ns = <300>;

		};

		opp@666667000 {

			opp-hz = /bits/ 64 <666667000>;

			clock-latency-ns = <300>;

		};

		opp@733334000 {

			opp-hz = /bits/ 64 <733334000>;

			clock-latency-ns = <300>;

		};

		opp@1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			clock-latency-ns = <300>;

		};

		opp@1100000000 {

			opp-hz = /bits/ 64 <1100000000>;

			clock-latency-ns = <300>;

		};

	};

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