drm/amdgpu: move umc ras fini to umc block (181c93e5) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+1 −11

Original line number	Diff line number	Diff line
		@@ -309,17 +309,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,

		void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
		{
		if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
		adev->umc.ras_if) {
		struct ras_common_if *ras_if = adev->umc.ras_if;
		struct ras_ih_if ih_info = {
		.head = *ras_if,
		.cb = amdgpu_umc_process_ras_data_cb,
		};

		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
		kfree(ras_if);
		}
		amdgpu_umc_ras_fini(adev);

		if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
		adev->mmhub.ras_if) {

+15 −0

Original line number	Diff line number	Diff line
		@@ -74,6 +74,21 @@ free:
		return r;
		}

		void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
		{
		if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
		adev->umc.ras_if) {
		struct ras_common_if *ras_if = adev->umc.ras_if;
		struct ras_ih_if ih_info = {
		.head = *ras_if,
		.cb = amdgpu_umc_process_ras_data_cb,
		};

		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
		kfree(ras_if);
		}
		}

		int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
		void *ras_error_status,
		struct amdgpu_iv_entry *entry)

+1 −0

Original line number	Diff line number	Diff line
		@@ -83,6 +83,7 @@ struct amdgpu_umc {
		};

		int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
		void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
		int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
		void *ras_error_status,
		struct amdgpu_iv_entry *entry);