Commit 17d0c106 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

Merge tag 'gvt-next-fixes-2020-03-31' of https://github.com/intel/gvt-linux... 

Merge tag 'gvt-next-fixes-2020-03-31' of https://github.com/intel/gvt-linux

 into drm-intel-next-fixes

gvt-next-fixes-2020-03-31

- Fix non-privilege access warning (Tina)
- Fix display port type (Tina)
- BDW cmd parser missed SWTESS_BASE_ADDRESS (Yan)
- Bypass length check of LRI (Yan)
- Fix one klocwork warning (Tina)

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200331070025.GB16629@zhen-hp.sh.intel.com
parents 2bdd4c28 eb0ff807

drivers/gpu/drm/i915/gvt/cmd_parser.c

+4 −12
Original line number Diff line number Diff line
@@ -164,6 +164,7 @@ struct decode_info { 
#define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)

#define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)

#define OP_3D_MEDIA_0_1_4			OP_3D_MEDIA(0x0, 0x1, 0x04)

#define OP_SWTESS_BASE_ADDRESS			OP_3D_MEDIA(0x0, 0x1, 0x03)



#define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
@@ -967,18 +968,6 @@ static int cmd_handler_lri(struct parser_exec_state *s) 
{

	int i, ret = 0;

	int cmd_len = cmd_length(s);

	u32 valid_len = CMD_LEN(1);



	/*

	 * Official intel docs are somewhat sloppy , check the definition of

	 * MI_LOAD_REGISTER_IMM.

	 */

	#define MAX_VALID_LEN 127

	if ((cmd_len < valid_len) || (cmd_len > MAX_VALID_LEN)) {

		gvt_err("len is not valid:  len=%u  valid_len=%u\n",

			cmd_len, valid_len);

		return -EFAULT;

	}



	for (i = 1; i < cmd_len; i += 2) {

		if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
@@ -2485,6 +2474,9 @@ static const struct cmd_info cmd_info[] = { 
	{"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,

		ADDR_FIX_1(1), 8, NULL},



	{"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS,

		F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},



	{"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},



	{"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/display.c

+3 −3
Original line number Diff line number Diff line
@@ -221,7 +221,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |

			TRANS_DDI_PORT_MASK);

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

			(PORT_B << TRANS_DDI_PORT_SHIFT) |

			TRANS_DDI_FUNC_ENABLE);

		if (IS_BROADWELL(dev_priv)) {
@@ -241,7 +241,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |

			TRANS_DDI_PORT_MASK);

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

			(PORT_C << TRANS_DDI_PORT_SHIFT) |

			TRANS_DDI_FUNC_ENABLE);

		if (IS_BROADWELL(dev_priv)) {
@@ -261,7 +261,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |

			TRANS_DDI_PORT_MASK);

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

			(PORT_D << TRANS_DDI_PORT_SHIFT) |

			TRANS_DDI_FUNC_ENABLE);

		if (IS_BROADWELL(dev_priv)) {

drivers/gpu/drm/i915/gvt/handlers.c

+6 −2
Original line number Diff line number Diff line
@@ -462,11 +462,14 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
	return 0;

}



/* ascendingly sorted */

/* sorted in ascending order */

static i915_reg_t force_nonpriv_white_list[] = {

	_MMIO(0xd80),

	GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)

	GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)

	CL_PRIMITIVES_COUNT, //_MMIO(0x2340)

	PS_INVOCATION_COUNT, //_MMIO(0x2348)

	PS_DEPTH_COUNT, //_MMIO(0x2350)

	GEN8_CS_CHICKEN1,//_MMIO(0x2580)

	_MMIO(0x2690),

	_MMIO(0x2694),
@@ -491,6 +494,7 @@ static i915_reg_t force_nonpriv_white_list[] = { 
	_MMIO(0xe18c),

	_MMIO(0xe48c),

	_MMIO(0xe5f4),

	_MMIO(0x64844),

};



/* a simple bsearch */

drivers/gpu/drm/i915/gvt/scheduler.c

+2 −2
Original line number Diff line number Diff line
@@ -296,8 +296,8 @@ shadow_context_descriptor_update(struct intel_context *ce, 
	 * Update bits 0-11 of the context descriptor which includes flags

	 * like GEN8_CTX_* cached in desc_template

	 */

	desc &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);

	desc |= workload->ctx_desc.addressing_mode <<

	desc &= ~(0x3ull << GEN8_CTX_ADDRESSING_MODE_SHIFT);

	desc |= (u64)workload->ctx_desc.addressing_mode <<

		GEN8_CTX_ADDRESSING_MODE_SHIFT;



	ce->lrc_desc = desc;

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