Merge tag 'usb-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Mixel DSI PHY for i.MX8

The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the

MIPI-DSI IP from Northwest Logic). It represents the physical layer for the

electrical signals for DSI.

Required properties:

- compatible: Must be:

  - "fsl,imx8mq-mipi-dphy"

- clocks: Must contain an entry for each entry in clock-names.

- clock-names: Must contain the following entries:

  - "phy_ref": phandle and specifier referring to the DPHY ref clock

- reg: the register range of the PHY controller

- #phy-cells: number of cells in PHY, as defined in

  Documentation/devicetree/bindings/phy/phy-bindings.txt

  this must be <0>

Optional properties:

- power-domains: phandle to power domain

Example:

	dphy: dphy@30a0030 {

		compatible = "fsl,imx8mq-mipi-dphy";

		clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;

		clock-names = "phy_ref";

		reg = <0x30a00300 0x100>;

		power-domains = <&pd_mipi0>;

		#phy-cells = <0>;

        };

	* "fsl,imx6sl-usbphy" for imx6sl

	* "fsl,vf610-usbphy" for Vybrid vf610

	* "fsl,imx6sx-usbphy" for imx6sx

	* "fsl,imx7ulp-usbphy" for imx7ulp

  "fsl,imx23-usbphy" is still a fallback for other strings

- reg: Should contain registers location and length

- interrupts: Should contain phy interrupt

  the 17.78mA TX reference current. Default: 100

Example:

usbphy1: usbphy@20c9000 {

usbphy1: usb-phy@20c9000 {

	compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";

	reg = <0x020c9000 0x1000>;

	interrupts = <0 44 0x04>;

- reset-names: Must include the following entries:

  - "padctl"

For Tegra124:

- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.

- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.

- avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.

- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.

For Tegra210:

- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.

- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.

- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.

- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.

For Tegra186:

- avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY

  power supply. Must supply 1.8 V.

Marvell PXA USB PHY

-------------------

Required properties:

- compatible: one of: "marvell,mmp2-usb-phy", "marvell,pxa910-usb-phy",

	"marvell,pxa168-usb-phy",

- #phy-cells: must be 0

Example:

	usb-phy: usbphy@d4207000 {

		compatible = "marvell,mmp2-usb-phy";

		reg = <0xd4207000 0x40>;

		#phy-cells = <0>;

		status = "okay";

	};

This document explains the device tree binding. For general

information about PHY subsystem refer to Documentation/phy.txt

Qualcomm PCIe2 PHY controller

=============================

The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm

platforms.

Required properties:

 - compatible: compatible list, should be:

	       "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"

 - reg: offset and length of the PHY register set.

 - #phy-cells: must be 0.

 - clocks: a clock-specifier pair for the "pipe" clock

 - vdda-vp-supply: phandle to low voltage regulator

 - vdda-vph-supply: phandle to high voltage regulator

 - resets: reset-specifier pairs for the "phy" and "pipe" resets

 - reset-names: list of resets, should contain:

		"phy" and "pipe"

 - clock-output-names: name of the outgoing clock signal from the PHY PLL

 - #clock-cells: must be 0

Example:

 phy@7786000 {

	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";

	reg = <0x07786000 0xb8>;

	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;

	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,

	         <&gcc GCC_PCIE_0_PIPE_ARES>;

	reset-names = "phy", "pipe";

	vdda-vp-supply = <&vreg_l3_1p05>;

	vdda-vph-supply = <&vreg_l5_1p8>;

	clock-output-names = "pcie_0_pipe_clk";

	#clock-cells = <0>;

	#phy-cells = <0>;

 };