Commit 179ac142 authored by Sumit Saxena's avatar Sumit Saxena Committed by Martin K. Petersen
Browse files

megaraid_sas: Reply Descriptor Post Queue (RDPQ) support 



This patch will create a reply queue pool for each MSI-X index and will
provide an array of base addresses instead of the single address of
legacy mode. Using this new interface the driver can support higher
queue depths through scattered DMA pools.

If array mode is not supported driver will fall back to the legacy
method of reply pool allocation. This limits controller queue depth to
1K max. To enable a queue depth of more than 1K driver requires firmware
to support array mode and scratch_pad3 will provide the new queue depth
value.

When RDPQ is used, downgrading to an older firmware release should not
be permitted. This may cause firmware fault and is not supported.

Signed-off-by: default avatarKashyap Desai <kashyap.desai@avagotech.com>
Signed-off-by: default avatarSumit Saxena <sumit.saxena@avagotech.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 8f05024c

drivers/scsi/megaraid/megaraid_sas.h

+5 −1
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ 
#define MFI_RESET_FLAGS				MFI_INIT_READY| \

						MFI_INIT_MFIMODE| \

						MFI_INIT_ABORT

#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)



/*

 * MFI frame flags
@@ -1416,6 +1417,7 @@ enum DCMD_TIMEOUT_ACTION { 
#define MR_MAX_REPLY_QUEUES_EXT_OFFSET          0X003FC000

#define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14

#define MR_MAX_MSIX_REG_ARRAY                   16

#define MR_RDPQ_MODE_OFFSET			0X00800000

/*

* register set for both 1068 and 1078 controllers

* structure extended for 1078 registers
@@ -1455,8 +1457,9 @@ struct megasas_register_set { 


	u32 	outbound_scratch_pad ;		/*00B0h*/

	u32	outbound_scratch_pad_2;         /*00B4h*/

	u32	outbound_scratch_pad_3;         /*00B8h*/



	u32	reserved_4[2];			/*00B8h*/

	u32	reserved_4;			/*00BCh*/



	u32 	inbound_low_queue_port ;	/*00C0h*/
@@ -2117,6 +2120,7 @@ struct megasas_instance { 
	u8 mask_interrupts;

	u16 max_chain_frame_sz;

	u8 is_imr;

	u8 is_rdpq;

	bool dev_handle;

};

struct MR_LD_VF_MAP {

drivers/scsi/megaraid/megaraid_sas_base.c

+9 −0
Original line number Diff line number Diff line
@@ -92,6 +92,10 @@ int smp_affinity_enable = 1; 
module_param(smp_affinity_enable, int, S_IRUGO);

MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)");



int rdpq_enable = 1;

module_param(rdpq_enable, int, S_IRUGO);

MODULE_PARM_DESC(rdpq_enable, " Allocate reply queue in chunks for large queue depth enable/disable Default: disable(0)");



MODULE_LICENSE("GPL");

MODULE_VERSION(MEGASAS_VERSION);

MODULE_AUTHOR("megaraidlinux.pdl@avagotech.com");
@@ -5080,6 +5084,9 @@ static int megasas_init_fw(struct megasas_instance *instance) 
				instance->msix_vectors = ((scratch_pad_2

					& MR_MAX_REPLY_QUEUES_EXT_OFFSET)

					>> MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT) + 1;

				if (rdpq_enable)

					instance->is_rdpq = (scratch_pad_2 & MR_RDPQ_MODE_OFFSET) ?

								1 : 0;

				fw_msix_count = instance->msix_vectors;

				/* Save 1-15 reply post index address to local memory

				 * Index 0 is already saved from reg offset
@@ -5116,6 +5123,8 @@ static int megasas_init_fw(struct megasas_instance *instance) 
	dev_info(&instance->pdev->dev,

		"current msix/online cpus\t: (%d/%d)\n",

		instance->msix_vectors, (unsigned int)num_online_cpus());

	dev_info(&instance->pdev->dev,

		"RDPQ mode\t: (%s)\n", instance->is_rdpq ? "enabled" : "disabled");



	tasklet_init(&instance->isr_tasklet, instance->instancet->tasklet,

		(unsigned long)instance);

drivers/scsi/megaraid/megaraid_sas_fusion.c

+307 −236

File changed.

Preview size limit exceeded, changes collapsed.

drivers/scsi/megaraid/megaraid_sas_fusion.h

+10 −2
Original line number Diff line number Diff line
@@ -928,6 +928,12 @@ struct MR_PD_CFG_SEQ_NUM_SYNC { 
	struct MR_PD_CFG_SEQ seq[1];

} __packed;



struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {

	u64 RDPQBaseAddress;

	u32 Reserved1;

	u32 Reserved2;

};



struct fusion_context {

	struct megasas_cmd_fusion **cmd_list;

	dma_addr_t req_frames_desc_phys;
@@ -940,8 +946,8 @@ struct fusion_context { 
	struct dma_pool *sg_dma_pool;

	struct dma_pool *sense_dma_pool;



	dma_addr_t reply_frames_desc_phys;

	union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc;

	dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];

	union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];

	struct dma_pool *reply_frames_desc_pool;



	u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
@@ -951,6 +957,8 @@ struct fusion_context { 
	u32 reply_alloc_sz;

	u32 io_frames_alloc_sz;



	struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;

	dma_addr_t rdpq_phys;

	u16	max_sge_in_main_msg;

	u16	max_sge_in_chain;

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