MIPS: mm: c-r4k: Panic if IL or DL fields have a reserved value (175cba8c) · Commits · 戴 / test

According to MIPS32 and MIPS64 PRA documents, a value of 7 in IL and DL fields is marked as "Reserved" so panic if the core uses this value in the config1 register. Also simplify the code a little bit. Signed-off-by:

Markos Chandras <markos.chandras@imgtec.com> Signed-off-by:

John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5861/

arch/mips/mm/c-r4k.c

+16 −8

Original line number	Diff line number	Diff line
		@@ -1013,10 +1013,14 @@ static void probe_pcache(void)
		*/
		config1 = read_c0_config1();

		if ((lsize = ((config1 >> 19) & 7)))
		c->icache.linesz = 2 << lsize;
		else
		c->icache.linesz = lsize;
		lsize = (config1 >> 19) & 7;

		/* IL == 7 is reserved */
		if (lsize == 7)
		panic("Invalid icache line size");

		c->icache.linesz = lsize ? 2 << lsize : 0;

		c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
		c->icache.ways = 1 + ((config1 >> 16) & 7);

		@@ -1033,10 +1037,14 @@ static void probe_pcache(void)
		*/
		c->dcache.flags = 0;

		if ((lsize = ((config1 >> 10) & 7)))
		c->dcache.linesz = 2 << lsize;
		else
		c->dcache.linesz= lsize;
		lsize = (config1 >> 10) & 7;

		/* DL == 7 is reserved */
		if (lsize == 7)
		panic("Invalid dcache line size");

		c->dcache.linesz = lsize ? 2 << lsize : 0;

		c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
		c->dcache.ways = 1 + ((config1 >> 7) & 7);

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