Commit 173da95d authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/psp11: simplify the ucode register logic 



Split it between navi10 and newer and everything before
navi10.

Reviewed-by: default avatarXiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f8a7976b

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

+2 −2
Original line number Diff line number Diff line
@@ -534,7 +534,7 @@ psp_v11_0_sram_map(struct amdgpu_device *adev, 


	case AMDGPU_UCODE_ID_RLC_G:

		*sram_offset = 0x2000;

		if (adev->asic_type != CHIP_NAVI10) {

		if (adev->asic_type < CHIP_NAVI10) {

			*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);

			*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);

		} else {
@@ -545,7 +545,7 @@ psp_v11_0_sram_map(struct amdgpu_device *adev, 


	case AMDGPU_UCODE_ID_SDMA0:

		*sram_offset = 0x0;

		if (adev->asic_type != CHIP_NAVI10) {

		if (adev->asic_type < CHIP_NAVI10) {

			*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);

			*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);

		} else {

CRA Git | Maintained and supported by SUSTech CRA and CCSE