Commit 171c2bcb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'core-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull unified TLB flushing from Ingo Molnar:
 "This contains the generic mmu_gather feature from Peter Zijlstra,
  which is an all-arch unification of TLB flushing APIs, via the
  following (broad) steps:

   - enhance the <asm-generic/tlb.h> APIs to cover more arch details

   - convert most TLB flushing arch implementations to the generic
     <asm-generic/tlb.h> APIs.

   - remove leftovers of per arch implementations

  After this series every single architecture makes use of the unified
  TLB flushing APIs"

* 'core-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  mm/resource: Use resource_overlaps() to simplify region_intersects()
  ia64/tlb: Eradicate tlb_migrate_finish() callback
  asm-generic/tlb: Remove tlb_table_flush()
  asm-generic/tlb: Remove tlb_flush_mmu_free()
  asm-generic/tlb: Remove CONFIG_HAVE_GENERIC_MMU_GATHER
  asm-generic/tlb: Remove arch_tlb*_mmu()
  s390/tlb: Convert to generic mmu_gather
  asm-generic/tlb: Introduce CONFIG_HAVE_MMU_GATHER_NO_GATHER=y
  arch/tlb: Clean up simple architectures
  um/tlb: Convert to generic mmu_gather
  sh/tlb: Convert SH to generic mmu_gather
  ia64/tlb: Convert to generic mmu_gather
  arm/tlb: Convert to generic mmu_gather
  asm-generic/tlb, arch: Invert CONFIG_HAVE_RCU_TABLE_INVALIDATE
  asm-generic/tlb, ia64: Conditionally provide tlb_migrate_finish()
  asm-generic/tlb: Provide generic tlb_flush() based on flush_tlb_mm()
  asm-generic/tlb, arch: Provide generic tlb_flush() based on flush_tlb_range()
  asm-generic/tlb, arch: Provide generic VIPT cache flush
  asm-generic/tlb, arch: Provide CONFIG_HAVE_MMU_GATHER_PAGE_SIZE
  asm-generic/tlb: Provide a comment
parents 423ea325 f6c6010a

Documentation/core-api/cachetlb.rst

+0 −10
Original line number Diff line number Diff line
@@ -101,16 +101,6 @@ changes occur: 
	translations for software managed TLB configurations.

	The sparc64 port currently does this.



6) ``void tlb_migrate_finish(struct mm_struct *mm)``



	This interface is called at the end of an explicit

	process migration. This interface provides a hook

	to allow a platform to update TLB or context-specific

	information for the address space.



	The ia64 sn2 platform is one example of a platform

	that uses this interface.



Next, we have the cache flushing interfaces.  In general, when Linux

is changing an existing virtual-->physical mapping to a new value,

the sequence will be in one of the following forms::

arch/Kconfig

+7 −1
Original line number Diff line number Diff line
@@ -383,7 +383,13 @@ config HAVE_ARCH_JUMP_LABEL_RELATIVE 
config HAVE_RCU_TABLE_FREE

	bool



config HAVE_RCU_TABLE_INVALIDATE

config HAVE_RCU_TABLE_NO_INVALIDATE

	bool



config HAVE_MMU_GATHER_PAGE_SIZE

	bool



config HAVE_MMU_GATHER_NO_GATHER

	bool



config ARCH_HAVE_NMI_SAFE_CMPXCHG

arch/alpha/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ config ALPHA 
	select ODD_RT_SIGACTION

	select OLD_SIGSUSPEND

	select CPU_NO_EFFICIENT_FFS if !ALPHA_EV67

	select MMU_GATHER_NO_RANGE

	help

	  The Alpha is a 64-bit general-purpose processor designed and

	  marketed by the Digital Equipment Corporation of blessed memory,

arch/alpha/include/asm/tlb.h

+0 −6
Original line number Diff line number Diff line
@@ -2,12 +2,6 @@ 
#ifndef _ALPHA_TLB_H

#define _ALPHA_TLB_H



#define tlb_start_vma(tlb, vma)			do { } while (0)

#define tlb_end_vma(tlb, vma)			do { } while (0)

#define __tlb_remove_tlb_entry(tlb, pte, addr)	do { } while (0)



#define tlb_flush(tlb)				flush_tlb_mm((tlb)->mm)



#include <asm-generic/tlb.h>



#define __pte_free_tlb(tlb, pte, address)		pte_free((tlb)->mm, pte)

arch/arc/include/asm/tlb.h

+0 −32
Original line number Diff line number Diff line
@@ -9,38 +9,6 @@ 
#ifndef _ASM_ARC_TLB_H

#define _ASM_ARC_TLB_H



#define tlb_flush(tlb)				\

do {						\

	if (tlb->fullmm)			\

		flush_tlb_mm((tlb)->mm);	\

} while (0)



/*

 * This pair is called at time of munmap/exit to flush cache and TLB entries

 * for mappings being torn down.

 * 1) cache-flush part -implemented via tlb_start_vma( ) for VIPT aliasing D$

 * 2) tlb-flush part - implemted via tlb_end_vma( ) flushes the TLB range

 *

 * Note, read http://lkml.org/lkml/2004/1/15/6

 */

#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING

#define tlb_start_vma(tlb, vma)

#else

#define tlb_start_vma(tlb, vma)						\

do {									\

	if (!tlb->fullmm)						\

		flush_cache_range(vma, vma->vm_start, vma->vm_end);	\

} while(0)

#endif



#define tlb_end_vma(tlb, vma)						\

do {									\

	if (!tlb->fullmm)						\

		flush_tlb_range(vma, vma->vm_start, vma->vm_end);	\

} while (0)



#define __tlb_remove_tlb_entry(tlb, ptep, address)



#include <linux/pagemap.h>

#include <asm-generic/tlb.h>

CRA Git | Maintained and supported by SUSTech CRA and CCSE