Commit 16ecd8d9 authored by Sasha Neftin's avatar Sasha Neftin Committed by Jeff Kirsher
Browse files

igc: Remove the obsolete workaround 



Enables a resend request after the completion timeout workaround is not
relevant for i225 device. This patch is clean code relevant this
workaround.
Minor cosmetic fixes, replace the 'spaces' with 'tabs'

Signed-off-by: default avatarSasha Neftin <sasha.neftin@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 796bfb10

drivers/net/ethernet/intel/igc/igc_base.c

+0 −49
Original line number Diff line number Diff line
@@ -9,50 +9,6 @@ 
#include "igc_base.h"

#include "igc.h"



/**

 * igc_set_pcie_completion_timeout - set pci-e completion timeout

 * @hw: pointer to the HW structure

 */

static s32 igc_set_pcie_completion_timeout(struct igc_hw *hw)

{

	u32 gcr = rd32(IGC_GCR);

	u16 pcie_devctl2;

	s32 ret_val = 0;



	/* only take action if timeout value is defaulted to 0 */

	if (gcr & IGC_GCR_CMPL_TMOUT_MASK)

		goto out;



	/* if capabilities version is type 1 we can write the

	 * timeout of 10ms to 200ms through the GCR register

	 */

	if (!(gcr & IGC_GCR_CAP_VER2)) {

		gcr |= IGC_GCR_CMPL_TMOUT_10ms;

		goto out;

	}



	/* for version 2 capabilities we need to write the config space

	 * directly in order to set the completion timeout value for

	 * 16ms to 55ms

	 */

	ret_val = igc_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,

					&pcie_devctl2);

	if (ret_val)

		goto out;



	pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;



	ret_val = igc_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,

					 &pcie_devctl2);

out:

	/* disable completion timeout resend */

	gcr &= ~IGC_GCR_CMPL_TMOUT_RESEND;



	wr32(IGC_GCR, gcr);



	return ret_val;

}



/**

 * igc_reset_hw_base - Reset hardware

 * @hw: pointer to the HW structure
@@ -72,11 +28,6 @@ static s32 igc_reset_hw_base(struct igc_hw *hw) 
	if (ret_val)

		hw_dbg("PCI-E Master disable polling has failed.\n");



	/* set the completion timeout for interface */

	ret_val = igc_set_pcie_completion_timeout(hw);

	if (ret_val)

		hw_dbg("PCI-E Set completion timeout has failed.\n");



	hw_dbg("Masking off all interrupts\n");

	wr32(IGC_IMC, 0xffffffff);

drivers/net/ethernet/intel/igc/igc_defines.h

+3 −9
Original line number Diff line number Diff line
@@ -29,12 +29,6 @@ 
/* Status of Master requests. */

#define IGC_STATUS_GIO_MASTER_ENABLE	0x00080000



/* PCI Express Control */

#define IGC_GCR_CMPL_TMOUT_MASK		0x0000F000

#define IGC_GCR_CMPL_TMOUT_10ms		0x00001000

#define IGC_GCR_CMPL_TMOUT_RESEND	0x00010000

#define IGC_GCR_CAP_VER2		0x00040000



/* Receive Address

 * Number of high/low register pairs in the RAR. The RAR (Receive Address

 * Registers) holds the directed and multicast addresses that we monitor.

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