Commit 16eaaee4 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-boards3-for-v3.10' of... 

Merge tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2

Third round of  Renesas ARM SoC board updates for v3.10

Highlights:

* Add Lager board support
* Add ape6evm board support
* Add Bock-W board support
* Mackerel MMCIF/SDHI clean ups
* Add ethernet support to kzm9g-reference

This pull request is based on a merge of:

git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux2-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards2-for-v3.10

The merge with renesas-pinmux2-for-v3.10 was made to provide
run-time dependencies for the following changes:

ARM: shmobile: APE6EVM LAN9220 support
ARM: shmobile: APE6EVM PFC support

* tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

: (307 commits)
  ARM: shmobile: mackerel: clean up MMCIF vs. SDHI1 selection
  ARM: shmobile: mackerel: add interrupt names for SDHI0
  ARM: shmobile: mackerel: switch SDHI and MMCIF interfaces to slot-gpio
  ARM: shmobile: mackerel: remove OCR masks, where regulators are used
  ARM: shmobile: mackerel: SDHI resources do not have to be numbered
  ARM: shmobile: Initial r8a7790 Lager board support
  ARM: shmobile: APE6EVM LAN9220 support
  ARM: shmobile: APE6EVM PFC support
  ARM: shmobile: APE6EVM base support
  ARM: shmobile: kzm9g-reference: add ethernet support
  ARM: shmobile: add R-Car M1A Bock-W platform support
  sh-pfc: r8a73a4: Remove unused GPIO bias data
  ARM: shmobile: r8a73a4: Remove all GPIO enums
  sh-pfc: r8a73a4: Remove function GPIOs
  ARM: shmobile: r8a73a4: Remove IRQC function GPIOs
  ARM: shmobile: r8a73a4: Remove SCIF function GPIOs
  sh-pfc: r8a73a4: Remove IRQC function GPIOS
  sh-pfc: r8a73a4: Remove SCIF function GPIOS
  sh-pfc: r8a73a4: Add IRQC pin groups and functions
  sh-pfc: r8a73a4: Add SCIF pin groups and functions
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 8bb96604 00ae962f

Documentation/devicetree/bindings/gpio/gpio.txt

+3 −3
Original line number Original line Diff line number Diff line
@@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example, 
		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";

		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";

		reg = <0x1460 0x18>;

		reg = <0x1460 0x18>;

		gpio-controller;

		gpio-controller;

		gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;

		gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;





    }

    }
@@ -107,8 +107,8 @@ where, 




   Next values specify the base pin and number of pins for the range

   Next values specify the base pin and number of pins for the range

   handled by 'qe_pio_e' gpio. In the given example from base pin 20 to

   handled by 'qe_pio_e' gpio. In the given example from base pin 20 to

   pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled

   pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under

   by this gpio controller.

   pinctrl2 with gpio offset 10 is handled by this gpio controller.





The pinctrl node must have "#gpio-range-cells" property to show number of

The pinctrl node must have "#gpio-range-cells" property to show number of

arguments to pass with phandle from gpio controllers node.
 
arguments to pass with phandle from gpio controllers node.

Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt

+106 −1
Original line number Original line Diff line number Diff line 
One-register-per-pin type device tree based pinctrl driver

One-register-per-pin type device tree based pinctrl driver





Required properties:

Required properties:

- compatible : "pinctrl-single"

- compatible : "pinctrl-single" or "pinconf-single".

  "pinctrl-single" means that pinconf isn't supported.

  "pinconf-single" means that generic pinconf is supported.





- reg : offset and length of the register set for the mux registers

- reg : offset and length of the register set for the mux registers
@@ -14,9 +16,61 @@ Optional properties: 
- pinctrl-single,function-off : function off mode for disabled state if

- pinctrl-single,function-off : function off mode for disabled state if

  available and same for all registers; if not specified, disabling of

  available and same for all registers; if not specified, disabling of

  pin functions is ignored

  pin functions is ignored



- pinctrl-single,bit-per-mux : boolean to indicate that one register controls

- pinctrl-single,bit-per-mux : boolean to indicate that one register controls

  more than one pin

  more than one pin





- pinctrl-single,drive-strength : array of value that are used to configure

  drive strength in the pinmux register. They're value of drive strength

  current and drive strength mask.



		/* drive strength current, mask */

		pinctrl-single,power-source = <0x30 0xf0>;



- pinctrl-single,bias-pullup : array of value that are used to configure the

  input bias pullup in the pinmux register.



		/* input, enabled pullup bits, disabled pullup bits, mask */

		pinctrl-single,bias-pullup = <0 1 0 1>;



- pinctrl-single,bias-pulldown : array of value that are used to configure the

  input bias pulldown in the pinmux register.



		/* input, enabled pulldown bits, disabled pulldown bits, mask */

		pinctrl-single,bias-pulldown = <2 2 0 2>;



  * Two bits to control input bias pullup and pulldown: User should use

    pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means

    pullup, and the other one bit means pulldown.

  * Three bits to control input bias enable, pullup and pulldown. User should

    use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias

    enable bit should be included in pullup or pulldown bits.

  * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as

    pinctrl-single,bias-disable. Because pinctrl single driver could implement

    it by calling pulldown, pullup disabled.



- pinctrl-single,input-schmitt : array of value that are used to configure

  input schmitt in the pinmux register. In some silicons, there're two input

  schmitt value (rising-edge & falling-edge) in the pinmux register.



		/* input schmitt value, mask */

		pinctrl-single,input-schmitt = <0x30 0x70>;



- pinctrl-single,input-schmitt-enable : array of value that are used to

  configure input schmitt enable or disable in the pinmux register.



		/* input, enable bits, disable bits, mask */

		pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;



- pinctrl-single,gpio-range : list of value that are used to configure a GPIO

  range. They're value of subnode phandle, pin base in pinctrl device, pin

  number in this range, GPIO function value of this GPIO range.

  The number of parameters is depend on #pinctrl-single,gpio-range-cells

  property.



		/* pin base, nr pins & gpio function */

		pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;



This driver assumes that there is only one register for each pin (unless the

This driver assumes that there is only one register for each pin (unless the

pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as

pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as

specified in the pinctrl-bindings.txt document in this directory.

specified in the pinctrl-bindings.txt document in this directory.
@@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the 
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to

device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to

be used when applying this change to the register.

be used when applying this change to the register.







Optional sub-node: In case some pins could be configured as GPIO in the pinmux

register, those pins could be defined as a GPIO range. This sub-node is required

by pinctrl-single,gpio-range property.



Required properties in sub-node:

- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in

  pinctrl-single,gpio-range property.



	range: gpio-range {

		#pinctrl-single,gpio-range-cells = <3>;

	};





Example:

Example:





/* SoC common file */

/* SoC common file */
@@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 { 
	pinctrl-single,function-mask = <0x5F>;

	pinctrl-single,function-mask = <0x5F>;

};

};





/* third controller instance for pins in gpio domain */

pmx_gpio: pinmux@d401e000 {

	compatible = "pinconf-single";

	reg = <0xd401e000 0x0330>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges;



	pinctrl-single,register-width = <32>;

	pinctrl-single,function-mask = <7>;



	/* sparse GPIO range could be supported */

	pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1

				&range 12 1 0 &range 13 29 1

				&range 43 1 0 &range 44 49 1

				&range 94 1 1 &range 96 2 1>;



	range: gpio-range {

		#pinctrl-single,gpio-range-cells = <3>;

	};

};





/* board specific .dts file */

/* board specific .dts file */





&pmx_core {

&pmx_core {
@@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 { 
		>;

		>;

	};

	};





	uart0_pins: pinmux_uart0_pins {

		pinctrl-single,pins = <

			0x208 0		/* UART0_RXD (IOCFG138) */

			0x20c 0		/* UART0_TXD (IOCFG139) */

		>;

		pinctrl-single,bias-pulldown = <0 2 2>;

		pinctrl-single,bias-pullup = <0 1 1>;

	};



	/* map uart2 pins */

	/* map uart2 pins */

	uart2_pins: pinmux_uart2_pins {

	uart2_pins: pinmux_uart2_pins {

		pinctrl-single,pins = <

		pinctrl-single,pins = <
@@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 { 




};

};





&uart1 {

       pinctrl-names = "default";

       pinctrl-0 = <&uart0_pins>;

};



&uart2 {

&uart2 {

       pinctrl-names = "default";

       pinctrl-names = "default";

       pinctrl-0 = <&uart2_pins>;

       pinctrl-0 = <&uart2_pins>;

arch/arm/Kconfig

+1 −1
Original line number Original line Diff line number Diff line
@@ -723,7 +723,7 @@ config ARCH_SHMOBILE 
	select MULTI_IRQ_HANDLER

	select MULTI_IRQ_HANDLER

	select NEED_MACH_MEMORY_H

	select NEED_MACH_MEMORY_H

	select NO_IOPORT

	select NO_IOPORT

	select PINCTRL

	select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB

	select PM_GENERIC_DOMAINS if PM

	select PM_GENERIC_DOMAINS if PM

	select SPARSE_IRQ

	select SPARSE_IRQ

	help

	help

arch/arm/boot/dts/Makefile

+5 −0
Original line number Original line Diff line number Diff line
@@ -136,7 +136,12 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ 
	ccu9540.dtb

	ccu9540.dtb

dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \

dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \

	r8a7740-armadillo800eva.dtb \

	r8a7740-armadillo800eva.dtb \

	r8a7778-bockw.dtb \

	r8a7779-marzen-reference.dtb \

	r8a7790-lager.dtb \

	sh73a0-kzm9g.dtb \

	sh73a0-kzm9g.dtb \

	sh73a0-kzm9g-reference.dtb \

	r8a73a4-ape6evm.dtb \

	sh7372-mackerel.dtb

	sh7372-mackerel.dtb

dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \

dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \

	socfpga_vt.dtb

	socfpga_vt.dtb

arch/arm/boot/dts/r8a73a4-ape6evm.dts

0 → 100644
+52 −0
Original line number Original line Diff line number Diff line 
/*

 * Device Tree Source for the APE6EVM board

 *

 * Copyright (C) 2013 Renesas Solutions Corp.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */



/dts-v1/;

/include/ "r8a73a4.dtsi"



/ {

	model = "APE6EVM";

	compatible = "renesas,ape6evm", "renesas,r8a73a4";



	chosen {

		bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp";

	};



	memory@40000000 {

		device_type = "memory";

		reg = <0 0x40000000 0 0x40000000>;

	};



	ape6evm_fixed_3v3: fixedregulator@0 {

		compatible = "regulator-fixed";

		regulator-name = "3V3";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-always-on;

	};



	lbsc {

		#address-cells = <1>;

		#size-cells = <1>;



		ethernet@8000000 {

			compatible = "smsc,lan9118", "smsc,lan9115";

			reg = <0x08000000 0x1000>;

			interrupt-parent = <&irqc1>;

			interrupts = <8 0x4>;

			phy-mode = "mii";

			reg-io-width = <4>;

			smsc,irq-active-high;

			smsc,irq-push-pull;

			vdd33a-supply = <&ape6evm_fixed_3v3>;

			vddvario-supply = <&ape6evm_fixed_3v3>;

		};

	};

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE