Commit 16e87459 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/gt: Move the batch buffer pool from the engine to the gt 



Since the introduction of 'soft-rc6', we aim to park the device quickly
and that results in frequent idling of the whole device. Currently upon
idling we free the batch buffer pool, and so this renders the cache
ineffective for many workloads. If we want to have an effective cache of
recently allocated buffers available for reuse, we need to decouple that
cache from the engine powermanagement and make it timer based. As there
is no reason then to keep it within the engine (where it once made
retirement order easier to track), we can move it up the hierarchy to the
owner of the memory allocations.

v2: Hook up to debugfs/drop_caches to clear the cache on demand.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200430111819.10262-2-chris@chris-wilson.co.uk
parent 230982d8

drivers/gpu/drm/i915/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -87,11 +87,11 @@ gt-y += \ 
	gt/intel_engine_cs.o \

	gt/intel_engine_heartbeat.o \

	gt/intel_engine_pm.o \

	gt/intel_engine_pool.o \

	gt/intel_engine_user.o \

	gt/intel_ggtt.o \

	gt/intel_ggtt_fencing.o \

	gt/intel_gt.o \

	gt/intel_gt_buffer_pool.o \

	gt/intel_gt_clock_utils.o \

	gt/intel_gt_irq.o \

	gt/intel_gt_pm.o \

drivers/gpu/drm/i915/gem/i915_gem_client_blt.c

+0 −1
Original line number Diff line number Diff line
@@ -6,7 +6,6 @@ 
#include "i915_drv.h"

#include "gt/intel_context.h"

#include "gt/intel_engine_pm.h"

#include "gt/intel_engine_pool.h"

#include "i915_gem_client_blt.h"

#include "i915_gem_object_blt.h"

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

+10 −10
Original line number Diff line number Diff line
@@ -15,8 +15,8 @@ 


#include "gem/i915_gem_ioctls.h"

#include "gt/intel_context.h"

#include "gt/intel_engine_pool.h"

#include "gt/intel_gt.h"

#include "gt/intel_gt_buffer_pool.h"

#include "gt/intel_gt_pm.h"

#include "gt/intel_ring.h"
@@ -1194,13 +1194,13 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, 
			     unsigned int len)

{

	struct reloc_cache *cache = &eb->reloc_cache;

	struct intel_engine_pool_node *pool;

	struct intel_gt_buffer_pool_node *pool;

	struct i915_request *rq;

	struct i915_vma *batch;

	u32 *cmd;

	int err;



	pool = intel_engine_get_pool(eb->engine, PAGE_SIZE);

	pool = intel_gt_get_buffer_pool(eb->engine->gt, PAGE_SIZE);

	if (IS_ERR(pool))

		return PTR_ERR(pool);
@@ -1229,7 +1229,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, 
		goto err_unpin;

	}



	err = intel_engine_pool_mark_active(pool, rq);

	err = intel_gt_buffer_pool_mark_active(pool, rq);

	if (err)

		goto err_request;
@@ -1270,7 +1270,7 @@ err_unpin: 
err_unmap:

	i915_gem_object_unpin_map(pool->obj);

out_pool:

	intel_engine_pool_put(pool);

	intel_gt_buffer_pool_put(pool);

	return err;

}
@@ -1887,7 +1887,7 @@ err_free: 
static int eb_parse(struct i915_execbuffer *eb)

{

	struct drm_i915_private *i915 = eb->i915;

	struct intel_engine_pool_node *pool;

	struct intel_gt_buffer_pool_node *pool;

	struct i915_vma *shadow, *trampoline;

	unsigned int len;

	int err;
@@ -1910,7 +1910,7 @@ static int eb_parse(struct i915_execbuffer *eb) 
		len += I915_CMD_PARSER_TRAMPOLINE_SIZE;

	}



	pool = intel_engine_get_pool(eb->engine, len);

	pool = intel_gt_get_buffer_pool(eb->engine->gt, len);

	if (IS_ERR(pool))

		return PTR_ERR(pool);
@@ -1958,7 +1958,7 @@ err_trampoline: 
err_shadow:

	i915_vma_unpin(shadow);

err:

	intel_engine_pool_put(pool);

	intel_gt_buffer_pool_put(pool);

	return err;

}
@@ -2643,7 +2643,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, 
	 */

	eb.request->batch = batch;

	if (batch->private)

		intel_engine_pool_mark_active(batch->private, eb.request);

		intel_gt_buffer_pool_mark_active(batch->private, eb.request);



	trace_i915_request_queue(eb.request, eb.batch_flags);

	err = eb_submit(&eb, batch);
@@ -2672,7 +2672,7 @@ err_batch_unpin: 
		i915_vma_unpin(batch);

err_parse:

	if (batch->private)

		intel_engine_pool_put(batch->private);

		intel_gt_buffer_pool_put(batch->private);

err_vma:

	if (eb.trampoline)

		i915_vma_unpin(eb.trampoline);

drivers/gpu/drm/i915/gem/i915_gem_object_blt.c

+9 −9
Original line number Diff line number Diff line
@@ -6,8 +6,8 @@ 
#include "i915_drv.h"

#include "gt/intel_context.h"

#include "gt/intel_engine_pm.h"

#include "gt/intel_engine_pool.h"

#include "gt/intel_gt.h"

#include "gt/intel_gt_buffer_pool.h"

#include "gt/intel_ring.h"

#include "i915_gem_clflush.h"

#include "i915_gem_object_blt.h"
@@ -18,7 +18,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, 
{

	struct drm_i915_private *i915 = ce->vm->i915;

	const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */

	struct intel_engine_pool_node *pool;

	struct intel_gt_buffer_pool_node *pool;

	struct i915_vma *batch;

	u64 offset;

	u64 count;
@@ -33,7 +33,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, 
	count = div_u64(round_up(vma->size, block_size), block_size);

	size = (1 + 8 * count) * sizeof(u32);

	size = round_up(size, PAGE_SIZE);

	pool = intel_engine_get_pool(ce->engine, size);

	pool = intel_gt_get_buffer_pool(ce->engine->gt, size);

	if (IS_ERR(pool)) {

		err = PTR_ERR(pool);

		goto out_pm;
@@ -96,7 +96,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, 
	return batch;



out_put:

	intel_engine_pool_put(pool);

	intel_gt_buffer_pool_put(pool);

out_pm:

	intel_engine_pm_put(ce->engine);

	return ERR_PTR(err);
@@ -114,13 +114,13 @@ int intel_emit_vma_mark_active(struct i915_vma *vma, struct i915_request *rq) 
	if (unlikely(err))

		return err;



	return intel_engine_pool_mark_active(vma->private, rq);

	return intel_gt_buffer_pool_mark_active(vma->private, rq);

}



void intel_emit_vma_release(struct intel_context *ce, struct i915_vma *vma)

{

	i915_vma_unpin(vma);

	intel_engine_pool_put(vma->private);

	intel_gt_buffer_pool_put(vma->private);

	intel_engine_pm_put(ce->engine);

}
@@ -213,7 +213,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, 
{

	struct drm_i915_private *i915 = ce->vm->i915;

	const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */

	struct intel_engine_pool_node *pool;

	struct intel_gt_buffer_pool_node *pool;

	struct i915_vma *batch;

	u64 src_offset, dst_offset;

	u64 count, rem;
@@ -228,7 +228,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, 
	count = div_u64(round_up(dst->size, block_size), block_size);

	size = (1 + 11 * count) * sizeof(u32);

	size = round_up(size, PAGE_SIZE);

	pool = intel_engine_get_pool(ce->engine, size);

	pool = intel_gt_get_buffer_pool(ce->engine->gt, size);

	if (IS_ERR(pool)) {

		err = PTR_ERR(pool);

		goto out_pm;
@@ -307,7 +307,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, 
	return batch;



out_put:

	intel_engine_pool_put(pool);

	intel_gt_buffer_pool_put(pool);

out_pm:

	intel_engine_pm_put(ce->engine);

	return ERR_PTR(err);

drivers/gpu/drm/i915/gem/i915_gem_object_blt.h

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 


#include "gt/intel_context.h"

#include "gt/intel_engine_pm.h"

#include "gt/intel_engine_pool.h"

#include "i915_vma.h"



struct drm_i915_gem_object;

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