Commit 16e6eea2 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.9-2020-08-07' of git://people.freedesktop.org/~agd5f/linux into drm-next 



amd-drm-fixes-5.9-2020-08-07:

amdgpu:
- Re-add spelling typo fix
- Sienna Cichlid fixes
- Navy Flounder fixes
- DC fixes
- SMU i2c fix
- Power fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200807222843.3909-1-alexander.deucher@amd.com
parents 15f9d8b8 f8781228

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+3 −1
Original line number Diff line number Diff line
@@ -2574,6 +2574,9 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) 
		AMD_IP_BLOCK_TYPE_IH,

	};



	for (i = 0; i < adev->num_ip_blocks; i++)

		adev->ip_blocks[i].status.hw = false;



	for (i = 0; i < ARRAY_SIZE(ip_order); i++) {

		int j;

		struct amdgpu_ip_block *block;
@@ -2581,7 +2584,6 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) 
		for (j = 0; j < adev->num_ip_blocks; j++) {

			block = &adev->ip_blocks[j];



			block->status.hw = false;

			if (block->version->type != ip_order[i] ||

				!block->status.valid)

				continue;

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+6 −0
Original line number Diff line number Diff line
@@ -3212,6 +3212,12 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, 
	     attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))

		return 0;



	/* Skip crit temp on APU */

	if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) &&

	    (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||

	     attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))

		return 0;



	/* Skip limit attributes if DPM is not enabled */

	if (!adev->pm.dpm_enabled &&

	    (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+30 −7
Original line number Diff line number Diff line
@@ -193,12 +193,18 @@ static int psp_sw_fini(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	psp_memory_training_fini(&adev->psp);

	if (adev->psp.sos_fw) {

		release_firmware(adev->psp.sos_fw);

		adev->psp.sos_fw = NULL;

	}

	if (adev->psp.asd_fw) {

		release_firmware(adev->psp.asd_fw);

		adev->psp.asd_fw = NULL;

	}

	if (adev->psp.ta_fw) {

		release_firmware(adev->psp.ta_fw);

		adev->psp.ta_fw = NULL;

	}



	if (adev->asic_type == CHIP_NAVI10)

		psp_sysfs_fini(adev);
@@ -409,11 +415,28 @@ static int psp_clear_vf_fw(struct psp_context *psp) 
	return ret;

}



static bool psp_skip_tmr(struct psp_context *psp)

{

	switch (psp->adev->asic_type) {

	case CHIP_NAVI12:

	case CHIP_SIENNA_CICHLID:

		return true;

	default:

		return false;

	}

}



static int psp_tmr_load(struct psp_context *psp)

{

	int ret;

	struct psp_gfx_cmd_resp *cmd;



	/* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.

	 * Already set up by host driver.

	 */

	if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))

		return 0;



	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);

	if (!cmd)

		return -ENOMEM;
@@ -1987,7 +2010,7 @@ static int psp_suspend(void *handle) 


	ret = psp_tmr_terminate(psp);

	if (ret) {

		DRM_ERROR("Falied to terminate tmr\n");

		DRM_ERROR("Failed to terminate tmr\n");

		return ret;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+4 −1
Original line number Diff line number Diff line
@@ -1618,7 +1618,7 @@ static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) 
	data = con->eh_data;

	save_count = data->count - control->num_recs;

	/* only new entries are saved */

	if (save_count > 0)

	if (save_count > 0) {

		if (amdgpu_ras_eeprom_process_recods(control,

							&data->bps[control->num_recs],

							true,
@@ -1627,6 +1627,9 @@ static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) 
			return -EIO;

		}



		dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);

	}



	return 0;

}

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+4 −3
Original line number Diff line number Diff line
@@ -3082,7 +3082,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
@@ -3127,7 +3127,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
@@ -3158,7 +3158,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xffffffff, 0x010b0000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)

};
@@ -7529,6 +7529,7 @@ static int gfx_v10_0_set_powergating_state(void *handle, 
	case CHIP_NAVI14:

	case CHIP_NAVI12:

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		amdgpu_gfx_off_ctrl(adev, enable);

		break;

	default:

CRA Git | Maintained and supported by SUSTech CRA and CCSE