Commit 16e024f3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

Pull powerpc update from Benjamin Herrenschmidt:
 "The main highlight is probably some base POWER8 support.  There's more
  to come such as transactional memory support but that will wait for
  the next one.

  Overall it's pretty quiet, or rather I've been pretty poor at picking
  things up from patchwork and reviewing them this time around and Kumar
  no better on the FSL side it seems..."

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (73 commits)
  powerpc+of: Rename and fix OF reconfig notifier error inject module
  powerpc: mpc5200: Add a3m071 board support
  powerpc/512x: don't compile any platform DIU code if the DIU is not enabled
  powerpc/mpc52xx: use module_platform_driver macro
  powerpc+of: Export of_reconfig_notifier_[register,unregister]
  powerpc/dma/raidengine: add raidengine device
  powerpc/iommu/fsl: Add PAMU bypass enable register to ccsr_guts struct
  powerpc/mpc85xx: Change spin table to cached memory
  powerpc/fsl-pci: Add PCI controller ATMU PM support
  powerpc/86xx: fsl_pcibios_fixup_bus requires CONFIG_PCI
  drivers/virt: the Freescale hypervisor driver doesn't need to check MSR[GS]
  powerpc/85xx: p1022ds: Use NULL instead of 0 for pointers
  powerpc: Disable relocation on exceptions when kexecing
  powerpc: Enable relocation on during exceptions at boot
  powerpc: Move get_longbusy_msecs into hvcall.h and remove duplicate function
  powerpc: Add wrappers to enable/disable relocation on exceptions
  powerpc: Add set_mode hcall
  powerpc: Setup relocation on exceptions for bare metal systems
  powerpc: Move initial mfspr LPCR out of __init_LPCR
  powerpc: Add relocation on exception vector handlers
  ...
parents c36e0501 376bddd3

Documentation/devicetree/bindings/powerpc/fsl/raideng.txt

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* Freescale 85xx RAID Engine nodes



RAID Engine nodes are defined to describe on-chip RAID accelerators.  Each RAID

Engine should have a separate node.



Supported chips:

P5020, P5040



Required properties:



- compatible:	Should contain "fsl,raideng-v1.0" as the value

		This identifies RAID Engine block. 1 in 1.0 represents

		major number whereas 0 represents minor number. The

		version matches the hardware IP version.

- reg:		offset and length of the register set for the device

- ranges:	standard ranges property specifying the translation

		between child address space and parent address space



Example:

	/* P5020 */

	raideng: raideng@320000 {

		compatible = "fsl,raideng-v1.0";

		#address-cells = <1>;

		#size-cells = <1>;

		reg	= <0x320000 0x10000>;

		ranges	= <0 0x320000 0x10000>;

	};





There must be a sub-node for each job queue present in RAID Engine

This node must be a sub-node of the main RAID Engine node



- compatible:	Should contain "fsl,raideng-v1.0-job-queue" as the value

		This identifies the job queue interface

- reg:		offset and length of the register set for job queue

- ranges:	standard ranges property specifying the translation

		between child address space and parent address space



Example:

	/* P5020 */

	raideng_jq0@1000 {

		compatible = "fsl,raideng-v1.0-job-queue";

		reg	   = <0x1000 0x1000>;

		ranges	   = <0x0 0x1000 0x1000>;

	};





There must be a sub-node for each job ring present in RAID Engine

This node must be a sub-node of job queue node



- compatible:	Must contain "fsl,raideng-v1.0-job-ring" as the value

		This identifies job ring. Should contain either

		"fsl,raideng-v1.0-hp-ring" or "fsl,raideng-v1.0-lp-ring"

		depending upon whether ring has high or low priority

- reg:		offset and length of the register set for job ring

- interrupts:	interrupt mapping for job ring IRQ



Optional property:



- fsl,liodn:	Specifies the LIODN to be used for Job Ring. This

		property is normally set by firmware. Value

		is of 12-bits which is the LIODN number for this JR.

		This property is used by the IOMMU (PAMU) to distinquish

		transactions from this JR and than be able to do address

		translation & protection accordingly.



Example:

	/* P5020 */

	raideng_jq0@1000 {

		compatible = "fsl,raideng-v1.0-job-queue";

		reg	   = <0x1000 0x1000>;

		ranges	   = <0x0 0x1000 0x1000>;



		raideng_jr0: jr@0 {

			compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";

			reg	   = <0x0 0x400>;

			interrupts = <139 2 0 0>;

			interrupt-parent = <&mpic>;

			fsl,liodn = <0x41>;

		};

	};

Documentation/powerpc/ptrace.txt

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@@ -127,6 +127,22 @@ Some examples of using the structure to: 
  p.addr2           = (uint64_t) end_range;

  p.condition_value = 0;



- set a watchpoint in server processors (BookS)



  p.version         = 1;

  p.trigger_type    = PPC_BREAKPOINT_TRIGGER_RW;

  p.addr_mode       = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;

  or

  p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;



  p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;

  p.addr            = (uint64_t) begin_range;

  /* For PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE addr2 needs to be specified, where

   * addr2 - addr <= 8 Bytes.

   */

  p.addr2           = (uint64_t) end_range;

  p.condition_value = 0;



3. PTRACE_DELHWDEBUG



Takes an integer which identifies an existing breakpoint or watchpoint

arch/arm/mach-mxs/mach-mxs.c

+1 −1
Original line number Diff line number Diff line
@@ -240,7 +240,7 @@ static void __init update_fec_mac_prop(enum mac_oui oui) 
		macaddr[4] = (val >> 8) & 0xff;

		macaddr[5] = (val >> 0) & 0xff;



		prom_update_property(np, newmac);

		of_update_property(np, newmac);

	}

}

arch/powerpc/Makefile

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@@ -181,7 +181,7 @@ $(BOOT_TARGETS2): vmlinux 
bootwrapper_install:

	$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)



%.dtb:

%.dtb: scripts

	$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)



define archhelp

arch/powerpc/boot/dts/a3m071.dts

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/*

 * a3m071 board Device Tree Source

 *

 * Copyright 2012 Stefan Roese <sr@denx.de>

 *

 * Copyright (C) 2011 DENX Software Engineering GmbH

 * Heiko Schocher <hs@denx.de>

 *

 * Copyright (C) 2007 Semihalf

 * Marian Balakowicz <m8@semihalf.com>

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */



/include/ "mpc5200b.dtsi"



/ {

	model = "anonymous,a3m071";

	compatible = "anonymous,a3m071";



	soc5200@f0000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "fsl,mpc5200b-immr";

		ranges = <0 0xf0000000 0x0000c000>;

		reg = <0xf0000000 0x00000100>;

		bus-frequency = <0>; /* From boot loader */

		system-frequency = <0>; /* From boot loader */



		timer@600 {

			fsl,has-wdt;

		};



		spi@f00 {

			status = "disabled";

		};



		usb: usb@1000 {

			status = "disabled";

		};



		psc@2000 {

			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";

			reg = <0x2000 0x100>;

			interrupts = <2 1 0>;

		};



		psc@2200 {

			status = "disabled";

		};



		psc@2400 {

			status = "disabled";

		};



		psc@2600 {

			status = "disabled";

		};



		psc@2800 {

			status = "disabled";

		};



		psc@2c00 {		// PSC6

			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";

			reg = <0x2c00 0x100>;

			interrupts = <2 4 0>;

		};



		ethernet@3000 {

			phy-handle = <&phy0>;

		};



		mdio@3000 {

			phy0: ethernet-phy@3 {

				reg = <0x03>;

			};

		};



		ata@3a00 {

			status = "disabled";

		};



		i2c@3d00 {

			status = "disabled";

		};



		i2c@3d40 {

			status = "disabled";

		};

	};



	localbus {

		compatible = "fsl,mpc5200b-lpb","simple-bus";

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0xfc000000 0x02000000

			  3 0 0xe9000000 0x00080000

			  5 0 0xe8000000 0x00010000>;



		flash@0,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0 0x0 0x02000000>;

			compatible = "cfi-flash";

			bank-width = <2>;

			partition@0x0 {

				label = "u-boot";

				reg = <0x00000000 0x00040000>;

				read-only;

			};

			partition@0x00040000 {

				label = "env";

				reg = <0x00040000 0x00020000>;

			};

			partition@0x00060000 {

				label = "dtb";

				reg = <0x00060000 0x00020000>;

			};

			partition@0x00080000 {

				label = "kernel";

				reg = <0x00080000 0x00500000>;

			};

			partition@0x00580000 {

				label = "root";

				reg = <0x00580000 0x00A80000>;

			};

		};



		fpga@3,0 {

			compatible = "anonymous,a3m071-fpga";

			reg = <3 0x0 0x00080000

			       5 0x0 0x00010000>;

			interrupts = <0 0 3>;  /* level low */

		};

	};



	pci@f0000d00 {

		status = "disabled";

	};

};

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