Commit 16bf121b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_fixes_5.9_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS fixes from Thomas Bogendoerfer:
 "A few MIPS fixes:

   - fallthrough fallout fix

   - BMIPS fixes

   - MSA fix to avoid leaking MSA register contents

   - Loongson perf and cpu feature fix

   - SNI interrupt fix"

* tag 'mips_fixes_5.9_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: SNI: Fix SCSI interrupt
  MIPS: add missing MSACSR and upper MSA initialization
  MIPS: perf: Fix wrong check condition of Loongson event IDs
  mips/oprofile: Fix fallthrough placement
  MIPS: Loongson64: Remove unnecessary inclusion of boot_param.h
  MIPS: BMIPS: Also call bmips_cpu_setup() for secondary cores
  MIPS: mm: BMIPS5000 has inclusive physical caches
  MIPS: Loongson64: Do not override watch and ejtag feature
parents 41bef91c baf5cb30

arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h

+0 −2
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@ 
#define cpu_has_counter		1

#define cpu_has_dc_aliases	(PAGE_SIZE < 0x4000)

#define cpu_has_divec		0

#define cpu_has_ejtag		0

#define cpu_has_inclusive_pcaches	1

#define cpu_has_llsc		1

#define cpu_has_mcheck		0
@@ -42,7 +41,6 @@ 
#define cpu_has_veic		0

#define cpu_has_vint		0

#define cpu_has_vtag_icache	0

#define cpu_has_watch		1

#define cpu_has_wsbh		1

#define cpu_has_ic_fills_f_dc	1

#define cpu_hwrena_impl_bits	0xc0000000

arch/mips/include/asm/mach-loongson64/irq.h

+0 −2
Original line number Diff line number Diff line
@@ -2,8 +2,6 @@ 
#ifndef __ASM_MACH_LOONGSON64_IRQ_H_

#define __ASM_MACH_LOONGSON64_IRQ_H_



#include <boot_param.h>



/* cpu core interrupt numbers */

#define NR_IRQS_LEGACY		16

#define NR_MIPS_CPU_IRQS	8

arch/mips/include/asm/mach-loongson64/mmzone.h

+0 −1
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ 
#ifndef _ASM_MACH_LOONGSON64_MMZONE_H

#define _ASM_MACH_LOONGSON64_MMZONE_H



#include <boot_param.h>

#define NODE_ADDRSPACE_SHIFT 44

#define NODE0_ADDRSPACE_OFFSET 0x000000000000UL

#define NODE1_ADDRSPACE_OFFSET 0x100000000000UL

arch/mips/kernel/perf_event_mipsxx.c

+2 −2
Original line number Diff line number Diff line
@@ -1898,8 +1898,8 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) 
				(base_id >= 64 && base_id < 90) ||

				(base_id >= 128 && base_id < 164) ||

				(base_id >= 192 && base_id < 200) ||

				(base_id >= 256 && base_id < 274) ||

				(base_id >= 320 && base_id < 358) ||

				(base_id >= 256 && base_id < 275) ||

				(base_id >= 320 && base_id < 361) ||

				(base_id >= 384 && base_id < 574))

				break;

arch/mips/kernel/smp-bmips.c

+2 −0
Original line number Diff line number Diff line
@@ -239,6 +239,8 @@ static int bmips_boot_secondary(int cpu, struct task_struct *idle) 
 */

static void bmips_init_secondary(void)

{

	bmips_cpu_setup();



	switch (current_cpu_type()) {

	case CPU_BMIPS4350:

	case CPU_BMIPS4380:

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