[MIPS] Fixup migration to GENERIC_TIME

  a) Implements functions required by Linux common code:

	time_init

	do_gettimeofday

	do_settimeofday

  b) provides an abstraction of RTC and null RTC implementation as default.

	extern unsigned long (*rtc_get_time)(void);

	extern int (*rtc_set_time)(unsigned long);

  c) a set of gettimeoffset functions for different CPUs and different

     needs.

  d) high-level and low-level timer interrupt routines where the timer 

  c) high-level and low-level timer interrupt routines where the timer

     interrupt source  may or may not be the CPU timer.  The high-level

     routine is dispatched through do_IRQ() while the low-level is

     dispatched in assemably code (usually int-handler.S)

  c) (optional) board-specific RTC routines.

  d) (optional) mips_hpt_frequency - It must be definied if the board

     is using CPU counter for timer interrupt or it is using fixed rate

     gettimeoffset().

     is using CPU counter for timer interrupt.

PORTING GUIDE

     If the answer is no, you need a timer to provide the timer interrupt

     at 100 HZ speed.

     You cannot use the fast gettimeoffset functions, i.e.,

	unsigned long fixed_rate_gettimeoffset(void);

	unsigned long calibrate_div32_gettimeoffset(void);

	unsigned long calibrate_div64_gettimeoffset(void);

    You can use null_gettimeoffset() will gives the same time resolution as

    jiffy.  Or you can implement your own gettimeoffset (probably based on 

    some ad hoc hardware on your machine.)

  c) The following sub steps assume your CPU has counter register.

     Do you plan to use the CPU counter register as the timer interrupt

     or use an exnternal timer?

  board_time_init() -

  	a) (optional) set up RTC routines,

        b) (optional) calibrate and set the mips_hpt_frequency

 	    (only needed if you intended to use fixed_rate_gettimeoffset

 	     or use cpu counter as timer interrupt source)

 	    (only needed if you intended to use cpu counter as timer interrupt

 	     source)

  plat_timer_setup() -

 	a) (optional) over-write any choices made above by time_init().

For example, you may define your own timer interrupt routine, which does

some of its own processing and then calls timer_interrupt().

You can also over-ride any of the built-in functions (gettimeoffset,

RTC routines and/or timer interrupt routine).

You can also over-ride any of the built-in functions (RTC routines

and/or timer interrupt routine).

PORTING NOTES FOR SMP

	You can also do the low-level version of those interrupt routines,

	following similar dispatching routes described above.

Note about do_gettimeoffset():

  It is very likely the CPU counter registers are not sync'ed up in a SMP box.

  Therefore you cannot really use the many of the existing routines that

  are based on CPU counter.  You should wirte your own gettimeoffset rouinte

  if you want intra-jiffy resolution.

int	no_au1xxx_32khz;

extern int allow_au1k_wait; /* default off for CP0 Counter */

/* Cycle counter value at the previous timer interrupt.. */

static unsigned int timerhi = 0, timerlo = 0;

#ifdef CONFIG_PM

#if HZ < 100 || HZ > 1000

#error "unsupported HZ value! Must be in [100,1000]"

		goto null;

	do {

		count = read_c0_count();

		timerhi += (count < timerlo);   /* Wrap around */

		timerlo = count;

		kstat_this_cpu.irqs[irq]++;

		do_timer(1);

#ifndef CONFIG_SMP

	return (cpu_speed / HZ);

}

/* This is for machines which generate the exact clock. */

#define USECS_PER_JIFFY (1000000/HZ)

#define USECS_PER_JIFFY_FRAC (0x100000000LL*1000000/HZ&0xffffffff)

static unsigned long

div64_32(unsigned long v1, unsigned long v2, unsigned long v3)

{

	unsigned long r0;

	do_div64_32(r0, v1, v2, v3);

	return r0;

}

static unsigned long do_fast_cp0_gettimeoffset(void)

{

	u32 count;

	unsigned long res, tmp;

	unsigned long r0;

	/* Last jiffy when do_fast_gettimeoffset() was called. */

	static unsigned long last_jiffies=0;

	unsigned long quotient;

	/*

	 * Cached "1/(clocks per usec)*2^32" value.

	 * It has to be recalculated once each jiffy.

	 */

	static unsigned long cached_quotient=0;

	tmp = jiffies;

	quotient = cached_quotient;

	if (tmp && last_jiffies != tmp) {

		last_jiffies = tmp;

		if (last_jiffies != 0) {

			r0 = div64_32(timerhi, timerlo, tmp);

			quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);

			cached_quotient = quotient;

		}

	}

	/* Get last timer tick in absolute kernel time */

	count = read_c0_count();

	/* .. relative to previous jiffy (32 bits is enough) */

	count -= timerlo;

	__asm__("multu\t%1,%2\n\t"

		"mfhi\t%0"

		: "=r" (res)

		: "r" (count), "r" (quotient)

		: "hi", "lo", GCC_REG_ACCUM);

	/*

	 * Due to possible jiffies inconsistencies, we need to check

	 * the result so that we'll get a timer that is monotonic.

	 */

	if (res >= USECS_PER_JIFFY)

		res = USECS_PER_JIFFY-1;

	return res;

}

#ifdef CONFIG_PM

static unsigned long do_fast_pm_gettimeoffset(void)

{

	unsigned long pc0;

	unsigned long offset;

	pc0 = au_readl(SYS_TOYREAD);

	au_sync();

	offset = pc0 - last_pc0;

	if (offset > 2*MATCH20_INC) {

		printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",

				(unsigned)offset, (unsigned)last_pc0,

				(unsigned)last_match20, (unsigned)pc0);

	}

	offset = (unsigned long)((offset * 305) / 10);

	return offset;

}

#endif

void __init plat_timer_setup(struct irqaction *irq)

{

	unsigned int est_freq;

		unsigned int c0_status;

		printk("WARNING: no 32KHz clock found.\n");

		do_gettimeoffset = do_fast_cp0_gettimeoffset;

		/* Ensure we get CPO_COUNTER interrupts.

		*/

		while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);

		startup_match20_interrupt(counter0_irq);

		do_gettimeoffset = do_fast_pm_gettimeoffset;

		/* We can use the real 'wait' instruction.

		*/

		allow_au1k_wait = 1;

	}

#else

	/* We have to do this here instead of in timer_init because

	 * the generic code in arch/mips/kernel/time.c will write

	 * over our function pointer.

	 */

	do_gettimeoffset = do_fast_cp0_gettimeoffset;

#endif

}

	return ioasic_read(IO_REG_FCTR);

}

static void dec_ioasic_hpt_init(unsigned int count)

{

	ioasic_write(IO_REG_FCTR, ioasic_read(IO_REG_FCTR) - count);

}

void __init dec_time_init(void)

{

	mips_timer_state = dec_timer_state;

	mips_timer_ack = dec_timer_ack;

	if (!cpu_has_counter && IOASIC) {

	if (!cpu_has_counter && IOASIC)

		/* For pre-R4k systems we use the I/O ASIC's counter.  */

		mips_hpt_read = dec_ioasic_hpt_read;

		mips_hpt_init = dec_ioasic_hpt_init;

	}

	/* Set up the rate of periodic DS1287 interrupts.  */

	CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);

	while (1);

}

static unsigned int jmr3927_hpt_read(void)

{

	/* We assume this function is called xtime_lock held. */

	return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;

}

#define USE_RTC_DS1742

#ifdef USE_RTC_DS1742

extern void rtc_ds1742_init(unsigned long base);

#endif

static void __init jmr3927_time_init(void)

{

	mips_hpt_read = jmr3927_hpt_read;

	mips_hpt_frequency = JMR3927_TIMER_CLK;

#ifdef USE_RTC_DS1742

	if (jmr3927_have_nvram()) {

	        rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);

#endif

}

unsigned long jmr3927_do_gettimeoffset(void);

void __init plat_timer_setup(struct irqaction *irq)

{

	do_gettimeoffset = jmr3927_do_gettimeoffset;

	jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;

	jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;

	jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;

#define USECS_PER_JIFFY (1000000/HZ)

unsigned long jmr3927_do_gettimeoffset(void)

{

       unsigned long count;

       unsigned long res = 0;

       /* MUST read TRR before TISR. */

       count = jmr3927_tmrptr->trr;

       if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {

               /* timer interrupt is pending.  use Max value. */

               res = USECS_PER_JIFFY - 1;

       } else {

               /* convert to usec */

               /* res = count / (JMR3927_TIMER_CLK / 1000000); */

               res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);

               /*

                * Due to possible jiffies inconsistencies, we need to check

                * the result so that we'll get a timer that is monotonic.

                */

               if (res >= USECS_PER_JIFFY)

                       res = USECS_PER_JIFFY-1;

       }

       return res;

}

//#undef DO_WRITE_THROUGH

#define DO_WRITE_THROUGH

#define DO_ENABLE_CACHE

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */

#include <linux/clocksource.h>

#include <linux/types.h>

#include <linux/kernel.h>

#include <linux/init.h>

int (*rtc_mips_set_mmss)(unsigned long);

/* usecs per counter cycle, shifted to left by 32 bits */

static unsigned int sll32_usecs_per_cycle;

/* how many counter cycles in a jiffy */

static unsigned long cycles_per_jiffy __read_mostly;

/* Cycle counter value at the previous timer interrupt.. */

static unsigned int timerhi, timerlo;

/* expirelo is the count value for next CPU timer interrupt */

static unsigned int expirelo;

	return 0;

}

static void null_hpt_init(unsigned int count)

static void __init null_hpt_init(void)

{

	/* nothing */

}

	return read_c0_count();

}

/* For use solely as a high precision timer.  */

static void c0_hpt_init(unsigned int count)

{

	write_c0_count(read_c0_count() - count);

}

/* For use both as a high precision timer and an interrupt source.  */

static void c0_hpt_timer_init(unsigned int count)

static void __init c0_hpt_timer_init(void)

{

	count = read_c0_count() - count;

	expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;

	write_c0_count(expirelo - cycles_per_jiffy);

	expirelo = read_c0_count() + cycles_per_jiffy;

	write_c0_compare(expirelo);

	write_c0_count(count);

}

int (*mips_timer_state)(void);

void (*mips_timer_ack)(void);

unsigned int (*mips_hpt_read)(void);

void (*mips_hpt_init)(unsigned int);

/*

 * Gettimeoffset routines.  These routines returns the time duration

 * since last timer interrupt in usecs.

 *

 * If the exact CPU counter frequency is known, use fixed_rate_gettimeoffset.

 * Otherwise use calibrate_gettimeoffset()

 *

 * If the CPU does not have the counter register, you can either supply

 * your own gettimeoffset() routine, or use null_gettimeoffset(), which

 * gives the same resolution as HZ.

 */

static unsigned long null_gettimeoffset(void)

{

	return 0;

}

/* The function pointer to one of the gettimeoffset funcs.  */

unsigned long (*do_gettimeoffset)(void) = null_gettimeoffset;

static unsigned long fixed_rate_gettimeoffset(void)

{

	u32 count;

	unsigned long res;

	/* Get last timer tick in absolute kernel time */

	count = mips_hpt_read();

	/* .. relative to previous jiffy (32 bits is enough) */

	count -= timerlo;

	__asm__("multu	%1,%2"

		: "=h" (res)

		: "r" (count), "r" (sll32_usecs_per_cycle)

		: "lo", GCC_REG_ACCUM);

	/*

	 * Due to possible jiffies inconsistencies, we need to check

	 * the result so that we'll get a timer that is monotonic.

	 */

	if (res >= USECS_PER_JIFFY)

		res = USECS_PER_JIFFY - 1;

	return res;

}

/*

 * Cached "1/(clocks per usec) * 2^32" value.

 * It has to be recalculated once each jiffy.

 */

static unsigned long cached_quotient;

/* Last jiffy when calibrate_divXX_gettimeoffset() was called. */

static unsigned long last_jiffies;

/*

 * This is moved from dec/time.c:do_ioasic_gettimeoffset() by Maciej.

 */

static unsigned long calibrate_div32_gettimeoffset(void)

{

	u32 count;

	unsigned long res, tmp;

	unsigned long quotient;

	tmp = jiffies;

	quotient = cached_quotient;

	if (last_jiffies != tmp) {

		last_jiffies = tmp;

		if (last_jiffies != 0) {

			unsigned long r0;

			do_div64_32(r0, timerhi, timerlo, tmp);

			do_div64_32(quotient, USECS_PER_JIFFY,

				    USECS_PER_JIFFY_FRAC, r0);

			cached_quotient = quotient;

		}

	}

	/* Get last timer tick in absolute kernel time */

	count = mips_hpt_read();

	/* .. relative to previous jiffy (32 bits is enough) */

	count -= timerlo;

	__asm__("multu  %1,%2"

		: "=h" (res)

		: "r" (count), "r" (quotient)

		: "lo", GCC_REG_ACCUM);

	/*

	 * Due to possible jiffies inconsistencies, we need to check

	 * the result so that we'll get a timer that is monotonic.

	 */

	if (res >= USECS_PER_JIFFY)

		res = USECS_PER_JIFFY - 1;

	return res;

}

static unsigned long calibrate_div64_gettimeoffset(void)

{

	u32 count;

	unsigned long res, tmp;

	unsigned long quotient;

	tmp = jiffies;

	quotient = cached_quotient;

	if (last_jiffies != tmp) {

		last_jiffies = tmp;

		if (last_jiffies) {

			unsigned long r0;

			__asm__(".set	push\n\t"

				".set	mips3\n\t"

				"lwu	%0,%3\n\t"

				"dsll32	%1,%2,0\n\t"

				"or	%1,%1,%0\n\t"

				"ddivu	$0,%1,%4\n\t"

				"mflo	%1\n\t"

				"dsll32	%0,%5,0\n\t"

				"or	%0,%0,%6\n\t"

				"ddivu	$0,%0,%1\n\t"

				"mflo	%0\n\t"

				".set	pop"

				: "=&r" (quotient), "=&r" (r0)

				: "r" (timerhi), "m" (timerlo),

				  "r" (tmp), "r" (USECS_PER_JIFFY),

				  "r" (USECS_PER_JIFFY_FRAC)

				: "hi", "lo", GCC_REG_ACCUM);

			cached_quotient = quotient;

		}

	}

	/* Get last timer tick in absolute kernel time */

	count = mips_hpt_read();

	/* .. relative to previous jiffy (32 bits is enough) */

	count -= timerlo;

	__asm__("multu	%1,%2"

		: "=h" (res)

		: "r" (count), "r" (quotient)

		: "lo", GCC_REG_ACCUM);

	/*

	 * Due to possible jiffies inconsistencies, we need to check

	 * the result so that we'll get a timer that is monotonic.

	 */

	if (res >= USECS_PER_JIFFY)

		res = USECS_PER_JIFFY - 1;

	return res;

}

void (*mips_hpt_init)(void) __initdata = null_hpt_init;

unsigned int mips_hpt_mask = 0xffffffff;

/* last time when xtime and rtc are sync'ed up */

static long last_rtc_update;

 */

irqreturn_t timer_interrupt(int irq, void *dev_id)

{

	unsigned long j;

	unsigned int count;

	write_seqlock(&xtime_lock);

	count = mips_hpt_read();

	mips_timer_ack();

	/* Update timerhi/timerlo for intra-jiffy calibration. */

	timerhi += count < timerlo;			/* Wrap around */

	timerlo = count;

	/*

	 * call the generic timer interrupt handling

	 */

		}

	}

	/*

	 * If jiffies has overflown in this timer_interrupt, we must

	 * update the timer[hi]/[lo] to make fast gettimeoffset funcs

	 * quotient calc still valid. -arca

	 *

	 * The first timer interrupt comes late as interrupts are

	 * enabled long after timers are initialized.  Therefore the

	 * high precision timer is fast, leading to wrong gettimeoffset()

	 * calculations.  We deal with it by setting it based on the

	 * number of its ticks between the second and the third interrupt.

	 * That is still somewhat imprecise, but it's a good estimate.

	 * --macro

	 */

	j = jiffies;

	if (j < 4) {

		static unsigned int prev_count;

		static int hpt_initialized;

		switch (j) {

		case 0:

			timerhi = timerlo = 0;

			mips_hpt_init(count);

			break;

		case 2:

			prev_count = count;

			break;

		case 3:

			if (!hpt_initialized) {

				unsigned int c3 = 3 * (count - prev_count);

				timerhi = 0;

				timerlo = c3;

				mips_hpt_init(count - c3);

				hpt_initialized = 1;

			}

			break;

		default:

			break;

		}

	}

	write_sequnlock(&xtime_lock);

	/*

 * 1) board_time_init() -

 * 	a) (optional) set up RTC routines,

 *      b) (optional) calibrate and set the mips_hpt_frequency

 *	    (only needed if you intended to use fixed_rate_gettimeoffset

 *	     or use cpu counter as timer interrupt source)

 *	    (only needed if you intended to use cpu counter as timer interrupt

 *	     source)

 * 2) setup xtime based on rtc_mips_get_time().

 * 3) choose a appropriate gettimeoffset routine.

 * 4) calculate a couple of cached variables for later usage

 * 5) plat_timer_setup() -

 * 3) calculate a couple of cached variables for later usage

 * 4) plat_timer_setup() -

 *	a) (optional) over-write any choices made above by time_init().

 *	b) machine specific code should setup the timer irqaction.

 *	c) enable the timer interrupt

	} while (--i);

	hpt_end = mips_hpt_read();

	hpt_count = hpt_end - hpt_start;

	hpt_count = (hpt_end - hpt_start) & mips_hpt_mask;

	hz = HZ;

	frequency = (u64)hpt_count * (u64)hz;

	return frequency >> log_2_loops;

}

static cycle_t read_mips_hpt(void)

{

	return (cycle_t)mips_hpt_read();

}

static struct clocksource clocksource_mips = {

	.name		= "MIPS",

	.read		= read_mips_hpt,

	.is_continuous	= 1,

};

static void __init init_mips_clocksource(void)

{

	u64 temp;

	u32 shift;

	if (!mips_hpt_frequency || mips_hpt_read == null_hpt_read)

		return;

	/* Calclate a somewhat reasonable rating value */

	clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;

	/* Find a shift value */

	for (shift = 32; shift > 0; shift--) {

		temp = (u64) NSEC_PER_SEC << shift;

		do_div(temp, mips_hpt_frequency);

		if ((temp >> 32) == 0)

			break;

	}

	clocksource_mips.shift = shift;

	clocksource_mips.mult = (u32)temp;

	clocksource_mips.mask = mips_hpt_mask;

	clocksource_register(&clocksource_mips);

}

void __init time_init(void)

{

	if (board_time_init)

	                        -xtime.tv_sec, -xtime.tv_nsec);

	/* Choose appropriate high precision timer routines.  */

	if (!cpu_has_counter && !mips_hpt_read) {

	if (!cpu_has_counter && !mips_hpt_read)

		/* No high precision timer -- sorry.  */

		mips_hpt_read = null_hpt_read;

		mips_hpt_init = null_hpt_init;

	} else if (!mips_hpt_frequency && !mips_timer_state) {

	else if (!mips_hpt_frequency && !mips_timer_state) {

		/* A high precision timer of unknown frequency.  */

		if (!mips_hpt_read) {

		if (!mips_hpt_read)

			/* No external high precision timer -- use R4k.  */

			mips_hpt_read = c0_hpt_read;

			mips_hpt_init = c0_hpt_init;

		}

		if (cpu_has_mips32r1 || cpu_has_mips32r2 ||

		    (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||

		    (current_cpu_data.isa_level == MIPS_CPU_ISA_II))

			/*

			 * We need to calibrate the counter but we don't have

			 * 64-bit division.

			 */

			do_gettimeoffset = calibrate_div32_gettimeoffset;

		else

			/*

			 * We need to calibrate the counter but we *do* have

			 * 64-bit division.

			 */

			do_gettimeoffset = calibrate_div64_gettimeoffset;

	} else {

		/* We know counter frequency.  Or we can get it.  */

		if (!mips_hpt_read) {

			/* No external high precision timer -- use R4k.  */

			mips_hpt_read = c0_hpt_read;

			if (mips_timer_state)

				mips_hpt_init = c0_hpt_init;

			else {

			if (!mips_timer_state) {

				/* No external timer interrupt -- use R4k.  */

				mips_hpt_init = c0_hpt_timer_init;

				mips_timer_ack = c0_timer_ack;

		if (!mips_hpt_frequency)

			mips_hpt_frequency = calibrate_hpt();

		do_gettimeoffset = fixed_rate_gettimeoffset;

		/* Calculate cache parameters.  */

		cycles_per_jiffy = (mips_hpt_frequency + HZ / 2) / HZ;

		/* sll32_usecs_per_cycle = 10^6 * 2^32 / mips_counter_freq  */

		do_div64_32(sll32_usecs_per_cycle,

			    1000000, mips_hpt_frequency / 2,

			    mips_hpt_frequency);

		/* Report the high precision timer rate for a reference.  */

		printk("Using %u.%03u MHz high precision timer.\n",

		       ((mips_hpt_frequency + 500) / 1000) / 1000,

		mips_timer_ack = null_timer_ack;

	/* This sets up the high precision timer for the first interrupt.  */

	mips_hpt_init(mips_hpt_read());

	mips_hpt_init();

	/*

	 * Call board specific timer interrupt setup.

	 * is not invoked accidentally.

	 */

	plat_timer_setup(&timer_irqaction);

	init_mips_clocksource();

}

#define FEBRUARY		2