clk: meson: meson8b: Make the CCF use the glitch-free VPU mux (16afd70a) · Commits · 戴 / test

The "vpu_0" or "vpu_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "vpu_0" and "vpu_1" gates. This makes the CCF switch to the "vpu_1" tree when "vpu_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the VPU clock. Signed-off-by:

Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:

Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200417184127.1319871-5-martin.blumenstingl@googlemail.com

drivers/clk/meson/meson8b.c

+11 −3

Original line number	Diff line number	Diff line
		@@ -2063,7 +2063,7 @@ static struct clk_regmap meson8b_vpu_0 = {
		&meson8b_vpu_0_div.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.flags = CLK_SET_RATE_GATE \| CLK_SET_RATE_PARENT,
		},
		};

		@@ -2134,10 +2134,18 @@ static struct clk_regmap meson8b_vpu_1 = {
		&meson8b_vpu_1_div.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.flags = CLK_SET_RATE_GATE \| CLK_SET_RATE_PARENT,
		},
		};

		/*
		* The VPU clock has two two identical clock trees (vpu_0 and vpu_1)
		* muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
		* actually manage this glitch-free mux because it does top-to-bottom
		* updates the each clock tree and switches to the "inactive" one when
		* CLK_SET_RATE_GATE is set.
		* Meson8 only has vpu_0 and no glitch-free mux.
		*/
		static struct clk_regmap meson8b_vpu = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_VPU_CLK_CNTL,
		@@ -2152,7 +2160,7 @@ static struct clk_regmap meson8b_vpu = {
		&meson8b_vpu_1.hw,
		},
		.num_parents = 2,
		.flags = CLK_SET_RATE_NO_REPARENT,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

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