Commit 169de131 authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
Browse files

drm/i915: PSR: Flush means invalidate + flush 



Since flush actually means invalidate + flush we need to force psr
exit on PSR flush.

On Core platforms there is no way to disable hw tracking and
do the pure sw tracking so we simulate it by fully disable psr and
reschedule a enable back.
So a good idea is to minimize sequential disable/enable in cases we
know that HW tracking like when flush has been originated by a flip.
Also flip had just invalidated it already.

It also uses origin to minimize the a bit the amount of
disable/enabled, mainly when flip already had invalidated.

With this patch in place it is possible to do a flush on dirty areas
properly in a following patch.

v2: Remove duplicated exit on HSW+Sprites as pointed out by Paulo.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent de152b62

drivers/gpu/drm/i915/intel_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -1329,7 +1329,8 @@ void intel_psr_disable(struct intel_dp *intel_dp); 
void intel_psr_invalidate(struct drm_device *dev,

			  unsigned frontbuffer_bits);

void intel_psr_flush(struct drm_device *dev,

		     unsigned frontbuffer_bits);

		     unsigned frontbuffer_bits,

		     enum fb_op_origin origin);

void intel_psr_init(struct drm_device *dev);

void intel_psr_single_frame_update(struct drm_device *dev,

				   unsigned frontbuffer_bits);

drivers/gpu/drm/i915/intel_frontbuffer.c

+1 −1
Original line number Diff line number Diff line
@@ -128,7 +128,7 @@ void intel_frontbuffer_flush(struct drm_device *dev, 
		return;



	intel_edp_drrs_flush(dev, frontbuffer_bits);

	intel_psr_flush(dev, frontbuffer_bits);

	intel_psr_flush(dev, frontbuffer_bits, origin);

	intel_fbc_flush(dev_priv, frontbuffer_bits);

}

drivers/gpu/drm/i915/intel_psr.c

+21 −19
Original line number Diff line number Diff line
@@ -680,6 +680,7 @@ void intel_psr_invalidate(struct drm_device *dev, 
 * intel_psr_flush - Flush PSR

 * @dev: DRM device

 * @frontbuffer_bits: frontbuffer plane tracking bits

 * @origin: which operation caused the flush

 *

 * Since the hardware frontbuffer tracking has gaps we need to integrate

 * with the software frontbuffer tracking. This function gets called every
@@ -689,7 +690,7 @@ void intel_psr_invalidate(struct drm_device *dev, 
 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.

 */

void intel_psr_flush(struct drm_device *dev,

		     unsigned frontbuffer_bits)

		     unsigned frontbuffer_bits, enum fb_op_origin origin)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_crtc *crtc;
@@ -707,24 +708,25 @@ void intel_psr_flush(struct drm_device *dev, 
	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);

	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;



	if (HAS_DDI(dev)) {

		/*

	 * On Haswell sprite plane updates don't result in a psr invalidating

	 * signal in the hardware. Which means we need to manually fake this in

	 * software for all flushes, not just when we've seen a preceding

	 * invalidation through frontbuffer rendering.

		 * By definition every flush should mean invalidate + flush,

		 * however on core platforms let's minimize the

		 * disable/re-enable so we can avoid the invalidate when flip

		 * originated the flush.

		 */

	if (IS_HASWELL(dev) &&

	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))

		if (frontbuffer_bits && origin != ORIGIN_FLIP)

			intel_psr_exit(dev);



	} else {

		/*

	 * On Valleyview and Cherryview we don't use hardware tracking so

	 * any plane updates or cursor moves don't result in a PSR

		 * On Valleyview and Cherryview we don't use hardware tracking

		 * so any plane updates or cursor moves don't result in a PSR

		 * invalidating. Which means we need to manually fake this in

	 * software for all flushes, not just when we've seen a preceding

	 * invalidation through frontbuffer rendering. */

	if (frontbuffer_bits && !HAS_DDI(dev))

		 * software for all flushes.

		 */

		if (frontbuffer_bits)

			intel_psr_exit(dev);

	}



	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)

		schedule_delayed_work(&dev_priv->psr.work,

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