Commit 167a4894 authored by Sean Christopherson's avatar Sean Christopherson Committed by Borislav Petkov
Browse files

x86/cpu: Set synthetic VMX cpufeatures during init_ia32_feat_ctl() 



Set the synthetic VMX cpufeatures, which need to be kept to preserve
/proc/cpuinfo's ABI, in the common IA32_FEAT_CTL initialization code.
Remove the vendor code that manually sets the synthetic flags.

Signed-off-by: default avatarSean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20191221044513.21680-13-sean.j.christopherson@intel.com
parent 14442a15

arch/x86/kernel/cpu/centaur.c

+0 −35
Original line number Diff line number Diff line
@@ -18,13 +18,6 @@ 
#define RNG_ENABLED	(1 << 3)

#define RNG_ENABLE	(1 << 6)	/* MSR_VIA_RNG */



#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000

#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000

#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000

#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001

#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002

#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020



static void init_c3(struct cpuinfo_x86 *c)

{

	u32  lo, hi;
@@ -119,31 +112,6 @@ static void early_init_centaur(struct cpuinfo_x86 *c) 
	}

}



static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)

{

	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;



	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);

	msr_ctl = vmx_msr_high | vmx_msr_low;



	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)

		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);

	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)

		set_cpu_cap(c, X86_FEATURE_VNMI);

	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {

		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,

		      vmx_msr_low, vmx_msr_high);

		msr_ctl2 = vmx_msr_high | vmx_msr_low;

		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&

		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))

			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);

		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)

			set_cpu_cap(c, X86_FEATURE_EPT);

		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)

			set_cpu_cap(c, X86_FEATURE_VPID);

	}

}



static void init_centaur(struct cpuinfo_x86 *c)

{

#ifdef CONFIG_X86_32
@@ -251,9 +219,6 @@ static void init_centaur(struct cpuinfo_x86 *c) 
#endif



	init_ia32_feat_ctl(c);



	if (cpu_has(c, X86_FEATURE_VMX))

		centaur_detect_vmx_virtcap(c);

}



#ifdef CONFIG_X86_32

arch/x86/kernel/cpu/feat_ctl.c

+14 −0
Original line number Diff line number Diff line
@@ -75,6 +75,20 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c) 
	    (c->vmx_capability[SECONDARY_CTLS] & VMX_F(VIRT_INTR_DELIVERY)) &&

	    (c->vmx_capability[MISC_FEATURES] & VMX_F(POSTED_INTR)))

		c->vmx_capability[MISC_FEATURES] |= VMX_F(APICV);



	/* Set the synthetic cpufeatures to preserve /proc/cpuinfo's ABI. */

	if (c->vmx_capability[PRIMARY_CTLS] & VMX_F(VIRTUAL_TPR))

		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);

	if (c->vmx_capability[MISC_FEATURES] & VMX_F(FLEXPRIORITY))

		set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);

	if (c->vmx_capability[MISC_FEATURES] & VMX_F(VIRTUAL_NMIS))

		set_cpu_cap(c, X86_FEATURE_VNMI);

	if (c->vmx_capability[SECONDARY_CTLS] & VMX_F(EPT))

		set_cpu_cap(c, X86_FEATURE_EPT);

	if (c->vmx_capability[MISC_FEATURES] & VMX_F(EPT_AD))

		set_cpu_cap(c, X86_FEATURE_EPT_AD);

	if (c->vmx_capability[MISC_FEATURES] & VMX_F(VPID))

		set_cpu_cap(c, X86_FEATURE_VPID);

}

#endif /* CONFIG_X86_VMX_FEATURE_NAMES */

arch/x86/kernel/cpu/intel.c

+0 −49
Original line number Diff line number Diff line
@@ -494,52 +494,6 @@ static void srat_detect_node(struct cpuinfo_x86 *c) 
#endif

}



static void detect_vmx_virtcap(struct cpuinfo_x86 *c)

{

	/* Intel VMX MSR indicated features */

#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000

#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000

#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000

#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001

#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002

#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020

#define x86_VMX_FEATURE_EPT_CAP_AD		0x00200000



	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;

	u32 msr_vpid_cap, msr_ept_cap;



	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);

	clear_cpu_cap(c, X86_FEATURE_VNMI);

	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);

	clear_cpu_cap(c, X86_FEATURE_EPT);

	clear_cpu_cap(c, X86_FEATURE_VPID);

	clear_cpu_cap(c, X86_FEATURE_EPT_AD);



	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);

	msr_ctl = vmx_msr_high | vmx_msr_low;

	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)

		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);

	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)

		set_cpu_cap(c, X86_FEATURE_VNMI);

	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {

		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,

		      vmx_msr_low, vmx_msr_high);

		msr_ctl2 = vmx_msr_high | vmx_msr_low;

		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&

		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))

			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);

		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) {

			set_cpu_cap(c, X86_FEATURE_EPT);

			rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,

			      msr_ept_cap, msr_vpid_cap);

			if (msr_ept_cap & x86_VMX_FEATURE_EPT_CAP_AD)

				set_cpu_cap(c, X86_FEATURE_EPT_AD);

		}

		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)

			set_cpu_cap(c, X86_FEATURE_VPID);

	}

}



#define MSR_IA32_TME_ACTIVATE		0x982



/* Helpers to access TME_ACTIVATE MSR */
@@ -757,9 +711,6 @@ static void init_intel(struct cpuinfo_x86 *c) 


	init_ia32_feat_ctl(c);



	if (cpu_has(c, X86_FEATURE_VMX))

		detect_vmx_virtcap(c);



	if (cpu_has(c, X86_FEATURE_TME))

		detect_tme(c);

arch/x86/kernel/cpu/zhaoxin.c

+0 −35
Original line number Diff line number Diff line
@@ -16,13 +16,6 @@ 
#define RNG_ENABLED	(1 << 3)

#define RNG_ENABLE	(1 << 8)	/* MSR_ZHAOXIN_RNG */



#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000

#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000

#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000

#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001

#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002

#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020



static void init_zhaoxin_cap(struct cpuinfo_x86 *c)

{

	u32  lo, hi;
@@ -89,31 +82,6 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c) 


}



static void zhaoxin_detect_vmx_virtcap(struct cpuinfo_x86 *c)

{

	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;



	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);

	msr_ctl = vmx_msr_high | vmx_msr_low;



	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)

		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);

	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)

		set_cpu_cap(c, X86_FEATURE_VNMI);

	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {

		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,

		      vmx_msr_low, vmx_msr_high);

		msr_ctl2 = vmx_msr_high | vmx_msr_low;

		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&

		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))

			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);

		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)

			set_cpu_cap(c, X86_FEATURE_EPT);

		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)

			set_cpu_cap(c, X86_FEATURE_VPID);

	}

}



static void init_zhaoxin(struct cpuinfo_x86 *c)

{

	early_init_zhaoxin(c);
@@ -142,9 +110,6 @@ static void init_zhaoxin(struct cpuinfo_x86 *c) 
#endif



	init_ia32_feat_ctl(c);



	if (cpu_has(c, X86_FEATURE_VMX))

		zhaoxin_detect_vmx_virtcap(c);

}



#ifdef CONFIG_X86_32

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