Merge tag 'usb-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next

DWC3- USB3 CONTROLLER

Required properties:

 - compatible: must be "synopsys,dwc3"

 - compatible: must be "snps,dwc3"

 - reg : Address and length of the register set for the device

 - interrupts: Interrupts used by the dwc3 controller.

 - usb-phy : array of phandle for the PHY device

 - usb-phy : array of phandle for the PHY device.  The first element

   in the array is expected to be a handle to the USB2/HS PHY and

   the second element is expected to be a handle to the USB3/SS PHY

Optional properties:

 - tx-fifo-resize: determines if the FIFO *has* to be reallocated.

This is usually a subnode to DWC3 glue to which it is connected.

dwc3@4a030000 {

	compatible = "synopsys,dwc3";

	compatible = "snps,dwc3";

	reg = <0x4a030000 0xcfff>;

	interrupts = <0 92 4>

	usb-phy = <&usb2_phy>, <&usb3,phy>;

Generic USB Properties

Optional properties:

 - maximum-speed: tells USB controllers we want to work up to a certain

			speed. Valid arguments are "super-speed", "high-speed",

			"full-speed" and "low-speed". In case this isn't passed

			via DT, USB controllers should default to their maximum

			HW capability.

 - dr_mode: tells Dual-Role USB controllers that we want to work on a

			particular mode. Valid arguments are "host",

			"peripheral" and "otg". In case this attribute isn't

			passed via DT, USB DRD controllers should default to

			OTG.

This is an attribute to a USB controller such as:

dwc3@4a030000 {

	compatible = "synopsys,dwc3";

	reg = <0x4a030000 0xcfff>;

	interrupts = <0 92 4>

	usb-phy = <&usb2_phy>, <&usb3,phy>;

	maximum-speed = "super-speed";

	dr_mode = "otg";

};

The device node for Tegra SOC USB PHY:

Required properties :

 - compatible : Should be "nvidia,tegra20-usb-phy".

 - compatible : Should be "nvidia,tegra<chip>-usb-phy".

 - reg : Defines the following set of registers, in the order listed:

   - The PHY's own register set.

     Always present.

Required properties for phy_type == ulpi:

  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.

Required PHY timing params for utmi phy:

Required PHY timing params for utmi phy, for all chips:

  - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before

    start of sync launches RxActive

  - nvidia,elastic-limit : Variable FIFO Depth of elastic input store

  - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait

    before declare IDLE.

  - nvidia,term-range-adj : Range adjusment on terminations

  - nvidia,xcvr-setup : HS driver output control

  - Either one of the following for HS driver output control:

    - nvidia,xcvr-setup : integer, uses the provided value.

    - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read

      from the on-chip fuses

    If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.

  - nvidia,xcvr-lsfslew : LS falling slew rate control.

  - nvidia,xcvr-lsrslew :  LS rising slew rate control.

Required PHY timing params for utmi phy, only on Tegra30 and above:

  - nvidia,xcvr-hsslew : HS slew rate control.

  - nvidia,hssquelch-level : HS squelch detector level.

  - nvidia,hsdiscon-level : HS disconnect detector level.

Optional properties:

  - nvidia,has-legacy-mode : boolean indicates whether this controller can

    operate in legacy mode (as APX 2500 / 2600). In legacy mode some

      peripheral means it is device controller

      otg means it can operate as either ("on the go")

Required properties for dr_mode == otg:

VBUS control (required for dr_mode == otg, optional for dr_mode == host):

  - vbus-supply: regulator for VBUS

Samsung High Speed USB OTG controller

-----------------------------

The Samsung HSOTG IP can be found on Samsung SoCs, from S3C6400 onwards.

It gives functionality of OTG-compliant USB 2.0 host and device with

support for USB 2.0 high-speed (480Mbps) and full-speed (12 Mbps)

operation.

Currently only device mode is supported.

Binding details

-----

Required properties:

- compatible: "samsung,s3c6400-hsotg" should be used for all currently

    supported SoC,

- interrupt-parent: phandle for the interrupt controller to which the

    interrupt signal of the HSOTG block is routed,

- interrupts: specifier of interrupt signal of interrupt controller,

    according to bindings of interrupt controller,

- clocks: contains an array of clock specifiers:

    - first entry: OTG clock

- clock-names: contains array of clock names:

    - first entry: must be "otg"

- vusb_d-supply: phandle to voltage regulator of digital section,

- vusb_a-supply: phandle to voltage regulator of analog section.

Example

-----

	hsotg@12480000 {

		compatible = "samsung,s3c6400-hsotg";

		reg = <0x12480000 0x20000>;

		interrupts = <0 71 0>;

		clocks = <&clock 305>;

		clock-names = "otg";

		vusb_d-supply = <&vusb_reg>;

		vusb_a-supply = <&vusbdac_reg>;

	};

			status = "okay";

		};

		musb: usb@47400000 {

			status = "okay";

			control@44e10000 {

				status = "okay";

			};

			phy@47401300 {

				status = "okay";

			};

			usb@47401000 {

				status = "okay";

			};

		};

		i2c0: i2c@44e0b000 {

			pinctrl-names = "default";

			pinctrl-0 = <&i2c0_pins>;