spi: Convert DW SPI binding to DT schema

Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.

Required properties:

- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or

  "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or

  "intel,keembay-ssi"

- reg : The register base for the controller. For "mscc,<soc>-spi", a second

  register set is required (named ICPU_CFG:SPI_MST)

- interrupts : One interrupt, used by the controller.

- #address-cells : <1>, as required by generic SPI binding.

- #size-cells : <0>, also as required by generic SPI binding.

- clocks : phandles for the clocks, see the description of clock-names below.

   The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock

   is optional. If a single clock is specified but no clock-name, it is the

   "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.

Optional properties:

- clock-names : Contains the names of the clocks:

    "ssi_clk", for the core clock used to generate the external SPI clock.

    "pclk", the interface clock, required for register access. If a clock domain

     used to enable this clock then it should be named "pclk_clkdomain".

- cs-gpios : Specifies the gpio pins to be used for chipselects.

- num-cs : The number of chipselects. If omitted, this will default to 4.

- reg-io-width : The I/O register width (in bytes) implemented by this

  device.  Supported values are 2 or 4 (the default).

- dmas : Phandle + identifiers of Tx and Rx DMA channels.

- dma-names : Contains the names of the DMA channels. Must be "tx" and "rx".

- resets : contains an entry for each entry in reset-names.

	   See ../reset/reset.txt for details.

- reset-names : must contain "spi"

Child nodes as per the generic SPI binding.

Example:

	spi@fff00000 {

		compatible = "snps,dw-apb-ssi";

		reg = <0xfff00000 0x1000>;

		interrupts = <0 154 4>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&spi_m_clk>;

		num-cs = <2>;

		cs-gpios = <&gpio0 13 0>,

			   <&gpio0 14 0>;

		resets = <&rst SPIM0_RST>;

		reset-names = "spi";

	};

# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface

maintainers:

  - Mark Brown <broonie@kernel.org>

allOf:

  - $ref: "spi-controller.yaml#"

  - if:

      properties:

        compatible:

          contains:

            enum:

              - mscc,ocelot-spi

              - mscc,jaguar2-spi

    then:

      properties:

        reg:

          minItems: 2

properties:

  compatible:

    oneOf:

      - description: Generic DW SPI Controller

        enum:

          - snps,dw-apb-ssi

          - snps,dwc-ssi-1.01a

      - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller

        items:

          - enum:

              - mscc,ocelot-spi

              - mscc,jaguar2-spi

          - const: snps,dw-apb-ssi

      - description: Amazon Alpine SPI Controller

        const: amazon,alpine-dw-apb-ssi

      - description: Renesas RZ/N1 SPI Controller

        items:

          - const: renesas,rzn1-spi

          - const: snps,dw-apb-ssi

      - description: Intel Keem Bay SPI Controller

        const: intel,keembay-ssi

  reg:

    minItems: 1

    items:

      - description: DW APB SSI controller memory mapped registers

      - description: SPI MST region map

  interrupts:

    maxItems: 1

  clocks:

    minItems: 1

    items:

      - description: SPI Controller reference clock source

      - description: APB interface clock source

  clock-names:

    minItems: 1

    items:

      - const: ssi_clk

      - const: pclk

  resets:

    maxItems: 1

  reset-names:

    const: spi

  reg-io-width:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: I/O register width (in bytes) implemented by this device

    default: 4

    enum: [ 2, 4 ]

  num-cs:

    default: 4

    minimum: 1

    maximum: 4

  dmas:

    items:

      - description: TX DMA Channel

      - description: RX DMA Channel

  dma-names:

    items:

      - const: tx

      - const: rx

patternProperties:

  "^.*@[0-9a-f]+$":

    type: object

    properties:

      reg:

        minimum: 0

        maximum: 3

      spi-rx-bus-width:

        const: 1

      spi-tx-bus-width:

        const: 1

unevaluatedProperties: false

required:

  - compatible

  - reg

  - "#address-cells"

  - "#size-cells"

  - interrupts

  - clocks

examples:

  - |

    spi@fff00000 {

      compatible = "snps,dw-apb-ssi";

      reg = <0xfff00000 0x1000>;

      #address-cells = <1>;

      #size-cells = <0>;

      interrupts = <0 154 4>;

      clocks = <&spi_m_clk>;

      num-cs = <2>;

      cs-gpios = <&gpio0 13 0>,

                 <&gpio0 14 0>;

    };

...

Synopsys DesignWare SPI master

Required properties:

- compatible: should be "snps,designware-spi"

- #address-cells: see spi-bus.txt

- #size-cells: see spi-bus.txt

- reg: address and length of the spi master registers

- interrupts: should contain one interrupt

- clocks: spi clock phandle

- num-cs: see spi-bus.txt

Optional properties:

- cs-gpios: see spi-bus.txt

Example:

spi: spi@4020a000 {

	compatible = "snps,designware-spi";

	interrupts = <11 1>;

	reg = <0x4020a000 0x1000>;

	clocks = <&pclk>;

	num-cs = <2>;

	cs-gpios = <&banka 0 0>;

};