Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (161f7a71) · Commits · 戴 / test

arch/x86/include/asm/hardirq.h

+0 −1

Original line number	Diff line number	Diff line
		@@ -7,7 +7,6 @@
		typedef struct {
		unsigned int __softirq_pending;
		unsigned int __nmi_count; /* arch dependent */
		unsigned int irq0_irqs;
		#ifdef CONFIG_X86_LOCAL_APIC
		unsigned int apic_timer_irqs; /* arch dependent */
		unsigned int irq_spurious_count;

arch/x86/kernel/time.c

+0 −3

Original line number	Diff line number	Diff line
		@@ -57,9 +57,6 @@ EXPORT_SYMBOL(profile_pc);
		*/
		static irqreturn_t timer_interrupt(int irq, void *dev_id)
		{
		/* Keep nmi watchdog up to date */
		inc_irq_stat(irq0_irqs);

		global_clock_event->event_handler(global_clock_event);

		/* MCA bus quirk: Acknowledge irq0 by setting bit 7 in port 0x61 */

arch/x86/kernel/tsc_sync.c

+24 −5

Original line number	Diff line number	Diff line
		@@ -42,7 +42,7 @@ static __cpuinitdata int nr_warps;
		/*
		* TSC-warp measurement loop running on both CPUs:
		*/
		static __cpuinit void check_tsc_warp(void)
		static __cpuinit void check_tsc_warp(unsigned int timeout)
		{
		cycles_t start, now, prev, end;
		int i;
		@@ -51,9 +51,9 @@ static __cpuinit void check_tsc_warp(void)
		start = get_cycles();
		rdtsc_barrier();
		/*
		* The measurement runs for 20 msecs:
		* The measurement runs for 'timeout' msecs:
		*/
		end = start + tsc_khz * 20ULL;
		end = start + (cycles_t) tsc_khz * timeout;
		now = start;

		for (i = 0; ; i++) {
		@@ -98,6 +98,25 @@ static __cpuinit void check_tsc_warp(void)
		now-start, end-start);
		}

		/*
		* If the target CPU coming online doesn't have any of its core-siblings
		* online, a timeout of 20msec will be used for the TSC-warp measurement
		* loop. Otherwise a smaller timeout of 2msec will be used, as we have some
		* information about this socket already (and this information grows as we
		* have more and more logical-siblings in that socket).
		*
		* Ideally we should be able to skip the TSC sync check on the other
		* core-siblings, if the first logical CPU in a socket passed the sync test.
		* But as the TSC is per-logical CPU and can potentially be modified wrongly
		* by the bios, TSC sync test for smaller duration should be able
		* to catch such errors. Also this will catch the condition where all the
		* cores in the socket doesn't get reset at the same time.
		*/
		static inline unsigned int loop_timeout(int cpu)
		{
		return (cpumask_weight(cpu_core_mask(cpu)) > 1) ? 2 : 20;
		}

		/*
		* Source CPU calls into this - it waits for the freshly booted
		* target CPU to arrive and then starts the measurement:
		@@ -135,7 +154,7 @@ void __cpuinit check_tsc_sync_source(int cpu)
		*/
		atomic_inc(&start_count);

		check_tsc_warp();
		check_tsc_warp(loop_timeout(cpu));

		while (atomic_read(&stop_count) != cpus-1)
		cpu_relax();
		@@ -183,7 +202,7 @@ void __cpuinit check_tsc_sync_target(void)
		while (atomic_read(&start_count) != cpus)
		cpu_relax();

		check_tsc_warp();
		check_tsc_warp(loop_timeout(smp_processor_id()));

		/*
		* Ok, we are done:

drivers/clocksource/acpi_pm.c

+16 −8

Original line number	Diff line number	Diff line
		@@ -23,6 +23,7 @@
		#include <linux/init.h>
		#include <linux/pci.h>
		#include <linux/delay.h>
		#include <linux/async.h>
		#include <asm/io.h>

		/*
		@@ -179,17 +180,15 @@ static int verify_pmtmr_rate(void)
		/* Number of reads we try to get two different values */
		#define ACPI_PM_READ_CHECKS 10000

		static int __init init_acpi_pm_clocksource(void)
		static void __init acpi_pm_clocksource_async(void *unused, async_cookie_t cookie)
		{
		cycle_t value1, value2;
		unsigned int i, j = 0;

		if (!pmtmr_ioport)
		return -ENODEV;

		/* "verify" this timing source: */
		for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) {
		udelay(100 * j);
		usleep_range(100 * j, 100 * j + 100);
		value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
		for (i = 0; i < ACPI_PM_READ_CHECKS; i++) {
		value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
		@@ -203,25 +202,34 @@ static int __init init_acpi_pm_clocksource(void)
		" 0x%#llx, 0x%#llx - aborting.\n",
		value1, value2);
		pmtmr_ioport = 0;
		return -EINVAL;
		return;
		}
		if (i == ACPI_PM_READ_CHECKS) {
		printk(KERN_INFO "PM-Timer failed consistency check "
		" (0x%#llx) - aborting.\n", value1);
		pmtmr_ioport = 0;
		return -ENODEV;
		return;
		}
		}

		if (verify_pmtmr_rate() != 0){
		pmtmr_ioport = 0;
		return -ENODEV;
		return;
		}

		return clocksource_register_hz(&clocksource_acpi_pm,
		clocksource_register_hz(&clocksource_acpi_pm,
		PMTMR_TICKS_PER_SEC);
		}

		static int __init init_acpi_pm_clocksource(void)
		{
		if (!pmtmr_ioport)
		return -ENODEV;

		async_schedule(acpi_pm_clocksource_async, NULL);
		return 0;
		}

		/* We use fs_initcall because we want the PCI fixups to have run
		* but we still need to load before device_initcall
		*/

drivers/clocksource/clksrc-dbx500-prcmu.c

+1 −4

Original line number	Diff line number	Diff line
		@@ -52,7 +52,6 @@ static struct clocksource clocksource_dbx500_prcmu = {
		.name = "dbx500-prcmu-timer",
		.rating = 300,
		.read = clksrc_dbx500_prcmu_read,
		.shift = 10,
		.mask = CLOCKSOURCE_MASK(32),
		.flags = CLOCK_SOURCE_IS_CONTINUOUS,
		};
		@@ -90,7 +89,5 @@ void __init clksrc_dbx500_prcmu_init(void __iomem *base)
		setup_sched_clock(dbx500_prcmu_sched_clock_read,
		32, RATE_32K);
		#endif
		clocksource_calc_mult_shift(&clocksource_dbx500_prcmu,
		RATE_32K, SCHED_CLOCK_MIN_WRAP);
		clocksource_register(&clocksource_dbx500_prcmu);
		clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
		}

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