Commit 1603b5ac authored by Atsushi Nemoto's avatar Atsushi Nemoto Committed by Ralf Baechle
Browse files

[MIPS] IRQ cleanups 



This is a big irq cleanup patch.

* Use set_irq_chip() to register irq_chip.
* Initialize .mask, .unmask, .mask_ack field.  Functions for these
  method are already exist in most case.
* Do not initialize .startup, .shutdown, .enable, .disable fields if
  default routines provided by irq_chip_set_defaults() were suitable.
* Remove redundant irq_desc initializations.
* Remove unnecessary local_irq_save/local_irq_restore, spin_lock.

With this cleanup, it would be easy to switch to slightly lightwait
irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ().

Though whole this patch is quite large, changes in each irq_chip are
not quite simple.  Please review and test on your platform.  Thanks.

Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c87b6eba

arch/mips/au1000/common/irq.c

+22 −41
Original line number Diff line number Diff line
@@ -70,7 +70,6 @@ extern irq_cpustat_t irq_stat [NR_CPUS]; 
extern void mips_timer_interrupt(void);



static void setup_local_irq(unsigned int irq, int type, int int_req);

static unsigned int startup_irq(unsigned int irq);

static void end_irq(unsigned int irq_nr);

static inline void mask_and_ack_level_irq(unsigned int irq_nr);

static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
@@ -84,20 +83,6 @@ void (*board_init_irq)(void); 
static DEFINE_SPINLOCK(irq_lock);





static unsigned int startup_irq(unsigned int irq_nr)

{

	local_enable_irq(irq_nr);

	return 0;

}





static void shutdown_irq(unsigned int irq_nr)

{

	local_disable_irq(irq_nr);

	return;

}





inline void local_enable_irq(unsigned int irq_nr)

{

	if (irq_nr > AU1000_LAST_INTC0_INT) {
@@ -249,41 +234,37 @@ void restore_local_and_enable(int controller, unsigned long mask) 


static struct irq_chip rise_edge_irq_type = {

	.typename = "Au1000 Rise Edge",

	.startup = startup_irq,

	.shutdown = shutdown_irq,

	.enable = local_enable_irq,

	.disable = local_disable_irq,

	.ack = mask_and_ack_rise_edge_irq,

	.mask = local_disable_irq,

	.mask_ack = mask_and_ack_rise_edge_irq,

	.unmask = local_enable_irq,

	.end = end_irq,

};



static struct irq_chip fall_edge_irq_type = {

	.typename = "Au1000 Fall Edge",

	.startup = startup_irq,

	.shutdown = shutdown_irq,

	.enable = local_enable_irq,

	.disable = local_disable_irq,

	.ack = mask_and_ack_fall_edge_irq,

	.mask = local_disable_irq,

	.mask_ack = mask_and_ack_fall_edge_irq,

	.unmask = local_enable_irq,

	.end = end_irq,

};



static struct irq_chip either_edge_irq_type = {

	.typename = "Au1000 Rise or Fall Edge",

	.startup = startup_irq,

	.shutdown = shutdown_irq,

	.enable = local_enable_irq,

	.disable = local_disable_irq,

	.ack = mask_and_ack_either_edge_irq,

	.mask = local_disable_irq,

	.mask_ack = mask_and_ack_either_edge_irq,

	.unmask = local_enable_irq,

	.end = end_irq,

};



static struct irq_chip level_irq_type = {

	.typename = "Au1000 Level",

	.startup = startup_irq,

	.shutdown = shutdown_irq,

	.enable = local_enable_irq,

	.disable = local_disable_irq,

	.ack = mask_and_ack_level_irq,

	.mask = local_disable_irq,

	.mask_ack = mask_and_ack_level_irq,

	.unmask = local_enable_irq,

	.end = end_irq,

};
@@ -328,31 +309,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 
				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);

				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);

				au_writel(1<<(irq_nr-32), IC1_CFG0SET);

				irq_desc[irq_nr].chip = &rise_edge_irq_type;

				set_irq_chip(irq_nr, &rise_edge_irq_type);

				break;

			case INTC_INT_FALL_EDGE: /* 0:1:0 */

				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);

				au_writel(1<<(irq_nr-32), IC1_CFG1SET);

				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);

				irq_desc[irq_nr].chip = &fall_edge_irq_type;

				set_irq_chip(irq_nr, &fall_edge_irq_type);

				break;

			case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */

				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);

				au_writel(1<<(irq_nr-32), IC1_CFG1SET);

				au_writel(1<<(irq_nr-32), IC1_CFG0SET);

				irq_desc[irq_nr].chip = &either_edge_irq_type;

				set_irq_chip(irq_nr, &either_edge_irq_type);

				break;

			case INTC_INT_HIGH_LEVEL: /* 1:0:1 */

				au_writel(1<<(irq_nr-32), IC1_CFG2SET);

				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);

				au_writel(1<<(irq_nr-32), IC1_CFG0SET);

				irq_desc[irq_nr].chip = &level_irq_type;

				set_irq_chip(irq_nr, &level_irq_type);

				break;

			case INTC_INT_LOW_LEVEL: /* 1:1:0 */

				au_writel(1<<(irq_nr-32), IC1_CFG2SET);

				au_writel(1<<(irq_nr-32), IC1_CFG1SET);

				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);

				irq_desc[irq_nr].chip = &level_irq_type;

				set_irq_chip(irq_nr, &level_irq_type);

				break;

			case INTC_INT_DISABLED: /* 0:0:0 */

				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
@@ -380,31 +361,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 
				au_writel(1<<irq_nr, IC0_CFG2CLR);

				au_writel(1<<irq_nr, IC0_CFG1CLR);

				au_writel(1<<irq_nr, IC0_CFG0SET);

				irq_desc[irq_nr].chip = &rise_edge_irq_type;

				set_irq_chip(irq_nr, &rise_edge_irq_type);

				break;

			case INTC_INT_FALL_EDGE: /* 0:1:0 */

				au_writel(1<<irq_nr, IC0_CFG2CLR);

				au_writel(1<<irq_nr, IC0_CFG1SET);

				au_writel(1<<irq_nr, IC0_CFG0CLR);

				irq_desc[irq_nr].chip = &fall_edge_irq_type;

				set_irq_chip(irq_nr, &fall_edge_irq_type);

				break;

			case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */

				au_writel(1<<irq_nr, IC0_CFG2CLR);

				au_writel(1<<irq_nr, IC0_CFG1SET);

				au_writel(1<<irq_nr, IC0_CFG0SET);

				irq_desc[irq_nr].chip = &either_edge_irq_type;

				set_irq_chip(irq_nr, &either_edge_irq_type);

				break;

			case INTC_INT_HIGH_LEVEL: /* 1:0:1 */

				au_writel(1<<irq_nr, IC0_CFG2SET);

				au_writel(1<<irq_nr, IC0_CFG1CLR);

				au_writel(1<<irq_nr, IC0_CFG0SET);

				irq_desc[irq_nr].chip = &level_irq_type;

				set_irq_chip(irq_nr, &level_irq_type);

				break;

			case INTC_INT_LOW_LEVEL: /* 1:1:0 */

				au_writel(1<<irq_nr, IC0_CFG2SET);

				au_writel(1<<irq_nr, IC0_CFG1SET);

				au_writel(1<<irq_nr, IC0_CFG0CLR);

				irq_desc[irq_nr].chip = &level_irq_type;

				set_irq_chip(irq_nr, &level_irq_type);

				break;

			case INTC_INT_DISABLED: /* 0:0:0 */

				au_writel(1<<irq_nr, IC0_CFG0CLR);

arch/mips/ddb5xxx/ddb5477/irq_5477.c

+5 −18
Original line number Diff line number Diff line
@@ -53,14 +53,6 @@ vrc5477_irq_disable(unsigned int irq) 
	ll_vrc5477_irq_disable(irq - vrc5477_irq_base);

}



static unsigned int vrc5477_irq_startup(unsigned int irq)

{

	vrc5477_irq_enable(irq);

	return 0;

}



#define	vrc5477_irq_shutdown	vrc5477_irq_disable



static void

vrc5477_irq_ack(unsigned int irq)

{
@@ -91,11 +83,10 @@ vrc5477_irq_end(unsigned int irq) 


struct irq_chip vrc5477_irq_controller = {

	.typename = "vrc5477_irq",

	.startup = vrc5477_irq_startup,

	.shutdown = vrc5477_irq_shutdown,

	.enable = vrc5477_irq_enable,

	.disable = vrc5477_irq_disable,

	.ack = vrc5477_irq_ack,

	.mask = vrc5477_irq_disable,

	.mask_ack = vrc5477_irq_ack,

	.unmask = vrc5477_irq_enable,

	.end = vrc5477_irq_end

};
@@ -103,12 +94,8 @@ void __init vrc5477_irq_init(u32 irq_base) 
{

	u32 i;



	for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) {

		irq_desc[i].status = IRQ_DISABLED;

		irq_desc[i].action = NULL;

		irq_desc[i].depth = 1;

		irq_desc[i].chip = &vrc5477_irq_controller;

	}

	for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++)

		set_irq_chip(i, &vrc5477_irq_controller);



	vrc5477_irq_base = irq_base;

}

arch/mips/dec/ecc-berr.c

+0 −6
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 
#include <linux/interrupt.h>

#include <linux/kernel.h>

#include <linux/sched.h>

#include <linux/spinlock.h>

#include <linux/types.h>



#include <asm/addrspace.h>
@@ -231,13 +230,10 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id) 
static inline void dec_kn02_be_init(void)

{

	volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);

	unsigned long flags;



	kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);

	kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);



	spin_lock_irqsave(&kn02_lock, flags);



	/* Preset write-only bits of the Control Register cache. */

	cached_kn02_csr = *csr | KN02_CSR_LEDS;
@@ -247,8 +243,6 @@ static inline void dec_kn02_be_init(void) 
	cached_kn02_csr |= KN02_CSR_CORRECT;

	*csr = cached_kn02_csr;

	iob();



	spin_unlock_irqrestore(&kn02_lock, flags);

}



static inline void dec_kn03_be_init(void)

arch/mips/dec/ioasic-irq.c

+13 −59
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ 


#include <linux/init.h>

#include <linux/irq.h>

#include <linux/spinlock.h>

#include <linux/types.h>



#include <asm/dec/ioasic.h>
@@ -21,8 +20,6 @@ 
#include <asm/dec/ioasic_ints.h>





static DEFINE_SPINLOCK(ioasic_lock);



static int ioasic_irq_base;
@@ -52,65 +49,31 @@ static inline void clear_ioasic_irq(unsigned int irq) 
	ioasic_write(IO_REG_SIR, sir);

}



static inline void enable_ioasic_irq(unsigned int irq)

{

	unsigned long flags;



	spin_lock_irqsave(&ioasic_lock, flags);

	unmask_ioasic_irq(irq);

	spin_unlock_irqrestore(&ioasic_lock, flags);

}



static inline void disable_ioasic_irq(unsigned int irq)

{

	unsigned long flags;



	spin_lock_irqsave(&ioasic_lock, flags);

	mask_ioasic_irq(irq);

	spin_unlock_irqrestore(&ioasic_lock, flags);

}





static inline unsigned int startup_ioasic_irq(unsigned int irq)

{

	enable_ioasic_irq(irq);

	return 0;

}



#define shutdown_ioasic_irq disable_ioasic_irq



static inline void ack_ioasic_irq(unsigned int irq)

{

	spin_lock(&ioasic_lock);

	mask_ioasic_irq(irq);

	spin_unlock(&ioasic_lock);

	fast_iob();

}



static inline void end_ioasic_irq(unsigned int irq)

{

	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))

		enable_ioasic_irq(irq);

		unmask_ioasic_irq(irq);

}



static struct irq_chip ioasic_irq_type = {

	.typename = "IO-ASIC",

	.startup = startup_ioasic_irq,

	.shutdown = shutdown_ioasic_irq,

	.enable = enable_ioasic_irq,

	.disable = disable_ioasic_irq,

	.ack = ack_ioasic_irq,

	.mask = mask_ioasic_irq,

	.mask_ack = ack_ioasic_irq,

	.unmask = unmask_ioasic_irq,

	.end = end_ioasic_irq,

};





#define startup_ioasic_dma_irq startup_ioasic_irq



#define shutdown_ioasic_dma_irq shutdown_ioasic_irq



#define enable_ioasic_dma_irq enable_ioasic_irq

#define unmask_ioasic_dma_irq unmask_ioasic_irq



#define disable_ioasic_dma_irq disable_ioasic_irq

#define mask_ioasic_dma_irq mask_ioasic_irq



#define ack_ioasic_dma_irq ack_ioasic_irq
@@ -123,11 +86,10 @@ static inline void end_ioasic_dma_irq(unsigned int irq) 


static struct irq_chip ioasic_dma_irq_type = {

	.typename = "IO-ASIC-DMA",

	.startup = startup_ioasic_dma_irq,

	.shutdown = shutdown_ioasic_dma_irq,

	.enable = enable_ioasic_dma_irq,

	.disable = disable_ioasic_dma_irq,

	.ack = ack_ioasic_dma_irq,

	.mask = mask_ioasic_dma_irq,

	.mask_ack = ack_ioasic_dma_irq,

	.unmask = unmask_ioasic_dma_irq,

	.end = end_ioasic_dma_irq,

};
@@ -140,18 +102,10 @@ void __init init_ioasic_irqs(int base) 
	ioasic_write(IO_REG_SIMR, 0);

	fast_iob();



	for (i = base; i < base + IO_INR_DMA; i++) {

		irq_desc[i].status = IRQ_DISABLED;

		irq_desc[i].action = 0;

		irq_desc[i].depth = 1;

		irq_desc[i].chip = &ioasic_irq_type;

	}

	for (; i < base + IO_IRQ_LINES; i++) {

		irq_desc[i].status = IRQ_DISABLED;

		irq_desc[i].action = 0;

		irq_desc[i].depth = 1;

		irq_desc[i].chip = &ioasic_dma_irq_type;

	}

	for (i = base; i < base + IO_INR_DMA; i++)

		set_irq_chip(i, &ioasic_irq_type);

	for (; i < base + IO_IRQ_LINES; i++)

		set_irq_chip(i, &ioasic_dma_irq_type);



	ioasic_irq_base = base;

}

arch/mips/dec/kn02-irq.c

+7 −46
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ 


#include <linux/init.h>

#include <linux/irq.h>

#include <linux/spinlock.h>

#include <linux/types.h>



#include <asm/dec/kn02.h>
@@ -29,7 +28,6 @@ 
 * There is no default value -- it has to be initialized.

 */

u32 cached_kn02_csr;

DEFINE_SPINLOCK(kn02_lock);





static int kn02_irq_base;
@@ -53,54 +51,24 @@ static inline void mask_kn02_irq(unsigned int irq) 
	*csr = cached_kn02_csr;

}



static inline void enable_kn02_irq(unsigned int irq)

{

	unsigned long flags;



	spin_lock_irqsave(&kn02_lock, flags);

	unmask_kn02_irq(irq);

	spin_unlock_irqrestore(&kn02_lock, flags);

}



static inline void disable_kn02_irq(unsigned int irq)

{

	unsigned long flags;



	spin_lock_irqsave(&kn02_lock, flags);

	mask_kn02_irq(irq);

	spin_unlock_irqrestore(&kn02_lock, flags);

}





static unsigned int startup_kn02_irq(unsigned int irq)

{

	enable_kn02_irq(irq);

	return 0;

}



#define shutdown_kn02_irq disable_kn02_irq



static void ack_kn02_irq(unsigned int irq)

{

	spin_lock(&kn02_lock);

	mask_kn02_irq(irq);

	spin_unlock(&kn02_lock);

	iob();

}



static void end_kn02_irq(unsigned int irq)

{

	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))

		enable_kn02_irq(irq);

		unmask_kn02_irq(irq);

}



static struct irq_chip kn02_irq_type = {

	.typename = "KN02-CSR",

	.startup = startup_kn02_irq,

	.shutdown = shutdown_kn02_irq,

	.enable = enable_kn02_irq,

	.disable = disable_kn02_irq,

	.ack = ack_kn02_irq,

	.mask = mask_kn02_irq,

	.mask_ack = ack_kn02_irq,

	.unmask = unmask_kn02_irq,

	.end = end_kn02_irq,

};
@@ -109,22 +77,15 @@ void __init init_kn02_irqs(int base) 
{

	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +

						       KN02_CSR);

	unsigned long flags;

	int i;



	/* Mask interrupts. */

	spin_lock_irqsave(&kn02_lock, flags);

	cached_kn02_csr &= ~KN02_CSR_IOINTEN;

	*csr = cached_kn02_csr;

	iob();

	spin_unlock_irqrestore(&kn02_lock, flags);



	for (i = base; i < base + KN02_IRQ_LINES; i++) {

		irq_desc[i].status = IRQ_DISABLED;

		irq_desc[i].action = 0;

		irq_desc[i].depth = 1;

		irq_desc[i].chip = &kn02_irq_type;

	}

	for (i = base; i < base + KN02_IRQ_LINES; i++)

		set_irq_chip(i, &kn02_irq_type);



	kn02_irq_base = base;

}

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