etnaviv: perfmon: fix total and idle HI cyleces readout (15ff4a7b) · Commits · 戴 / test

drivers/gpu/drm/etnaviv/etnaviv_perfmon.c

+33 −11

Original line number	Diff line number	Diff line
		@@ -4,6 +4,7 @@
		* Copyright (C) 2017 Zodiac Inflight Innovations
		*/

		#include "common.xml.h"
		#include "etnaviv_gpu.h"
		#include "etnaviv_perfmon.h"
		#include "state_hi.xml.h"
		@@ -35,13 +36,6 @@ struct etnaviv_pm_domain_meta {
		u32 nr_domains;
		};

		static u32 simple_reg_read(struct etnaviv_gpu *gpu,
		const struct etnaviv_pm_domain *domain,
		const struct etnaviv_pm_signal *signal)
		{
		return gpu_read(gpu, signal->data);
		}

		static u32 perf_reg_read(struct etnaviv_gpu *gpu,
		const struct etnaviv_pm_domain *domain,
		const struct etnaviv_pm_signal *signal)
		@@ -75,6 +69,34 @@ static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
		return value;
		}

		static u32 hi_total_cycle_read(struct etnaviv_gpu *gpu,
		const struct etnaviv_pm_domain *domain,
		const struct etnaviv_pm_signal *signal)
		{
		u32 reg = VIVS_HI_PROFILE_TOTAL_CYCLES;

		if (gpu->identity.model == chipModel_GC880 \|\|
		gpu->identity.model == chipModel_GC2000 \|\|
		gpu->identity.model == chipModel_GC2100)
		reg = VIVS_MC_PROFILE_CYCLE_COUNTER;

		return gpu_read(gpu, reg);
		}

		static u32 hi_total_idle_cycle_read(struct etnaviv_gpu *gpu,
		const struct etnaviv_pm_domain *domain,
		const struct etnaviv_pm_signal *signal)
		{
		u32 reg = VIVS_HI_PROFILE_IDLE_CYCLES;

		if (gpu->identity.model == chipModel_GC880 \|\|
		gpu->identity.model == chipModel_GC2000 \|\|
		gpu->identity.model == chipModel_GC2100)
		reg = VIVS_HI_PROFILE_TOTAL_CYCLES;

		return gpu_read(gpu, reg);
		}

		static const struct etnaviv_pm_domain doms_3d[] = {
		{
		.name = "HI",
		@@ -84,13 +106,13 @@ static const struct etnaviv_pm_domain doms_3d[] = {
		.signal = (const struct etnaviv_pm_signal[]) {
		{
		"TOTAL_CYCLES",
		VIVS_HI_PROFILE_TOTAL_CYCLES,
		&simple_reg_read
		0,
		&hi_total_cycle_read
		},
		{
		"IDLE_CYCLES",
		VIVS_HI_PROFILE_IDLE_CYCLES,
		&simple_reg_read
		0,
		&hi_total_idle_cycle_read
		},
		{
		"AXI_CYCLES_READ_REQUEST_STALLED",

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